derek.holloway
7502bf64a4
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30 lines
1.1 KiB
LLVM
30 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn--amdhsa -mcpu=hawaii < %s | FileCheck -check-prefix=GCN %s
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define amdgpu_kernel void @test_wave64(i32 %arg0, [8 x i32], i64 %saved) {
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; GCN-LABEL: test_wave64:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dword s2, s[8:9], 0x0
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0xa
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; GCN-NEXT: s_add_i32 s12, s12, s17
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; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
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; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_cmp_eq_u32 s2, 0
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; GCN-NEXT: s_cselect_b64 s[2:3], exec, 0
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; GCN-NEXT: s_and_b64 s[2:3], exec, s[2:3]
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; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_endpgm
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entry:
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%cond = icmp eq i32 %arg0, 0
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%break = call i64 @llvm.amdgcn.if.break.i64(i1 %cond, i64 %saved)
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store volatile i64 %break, ptr addrspace(1) poison
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ret void
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}
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declare i64 @llvm.amdgcn.if.break.i64(i1, i64)
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