derek.holloway
7502bf64a4
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233 lines
8.3 KiB
LLVM
233 lines
8.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
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define i32 @mul_u24_s32_divergent(i32 %a, i32 %b) {
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; GFX9-LABEL: mul_u24_s32_divergent:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: mul_u24_s32_divergent:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mul_u32_u24_e32 v0, v0, v1
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%result = call i32 @llvm.amdgcn.mul.u24.i32(i32 %a, i32 %b)
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ret i32 %result
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}
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define amdgpu_ps i32 @mul_u24_s32_uniform(i32 inreg %a, i32 inreg %b) {
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; GFX9-LABEL: mul_u24_s32_uniform:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v0, s1
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; GFX9-NEXT: v_mul_u32_u24_e32 v0, s0, v0
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; GFX9-NEXT: v_readfirstlane_b32 s0, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mul_u24_s32_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mul_u32_u24_e64 v0, s0, s1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v0
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; GFX11-NEXT: ; return to shader part epilog
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%result = call i32 @llvm.amdgcn.mul.u24.i32(i32 %a, i32 %b)
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ret i32 %result
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}
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define i64 @mul_u24_s64_divergent(i32 %a, i32 %b) {
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; GFX9-LABEL: mul_u24_s64_divergent:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mul_hi_u32_u24_e32 v2, v0, v1
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; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v1
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; GFX9-NEXT: v_mov_b32_e32 v1, v2
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: mul_u24_s64_divergent:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mul_u32_u24_e32 v2, v0, v1
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; GFX11-NEXT: v_mul_hi_u32_u24_e32 v1, v0, v1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX11-NEXT: v_mov_b32_e32 v0, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%result = call i64 @llvm.amdgcn.mul.u24.i64(i32 %a, i32 %b)
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ret i64 %result
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}
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define amdgpu_ps i64 @mul_u24_s64_uniform(i32 inreg %a, i32 inreg %b) {
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; GFX9-LABEL: mul_u24_s64_uniform:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v0, s1
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; GFX9-NEXT: v_mul_hi_u32_u24_e32 v1, s0, v0
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; GFX9-NEXT: v_mul_u32_u24_e32 v0, s0, v0
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; GFX9-NEXT: v_readfirstlane_b32 s0, v0
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; GFX9-NEXT: v_readfirstlane_b32 s1, v1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mul_u24_s64_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mul_u32_u24_e64 v0, s0, s1
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; GFX11-NEXT: v_mul_hi_u32_u24_e64 v1, s0, s1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v0
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; GFX11-NEXT: v_readfirstlane_b32 s1, v1
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; GFX11-NEXT: ; return to shader part epilog
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%result = call i64 @llvm.amdgcn.mul.u24.i64(i32 %a, i32 %b)
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ret i64 %result
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}
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define i32 @mul_i24_s32_divergent(i32 %a, i32 %b) {
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; GFX9-LABEL: mul_i24_s32_divergent:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: mul_i24_s32_divergent:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mul_i32_i24_e32 v0, v0, v1
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%result = call i32 @llvm.amdgcn.mul.i24.i32(i32 %a, i32 %b)
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ret i32 %result
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}
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define amdgpu_ps i32 @mul_i24_s32_uniform(i32 inreg %a, i32 inreg %b) {
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; GFX9-LABEL: mul_i24_s32_uniform:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v0, s1
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; GFX9-NEXT: v_mul_i32_i24_e32 v0, s0, v0
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; GFX9-NEXT: v_readfirstlane_b32 s0, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mul_i24_s32_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mul_i32_i24_e64 v0, s0, s1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v0
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; GFX11-NEXT: ; return to shader part epilog
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%result = call i32 @llvm.amdgcn.mul.i24.i32(i32 %a, i32 %b)
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ret i32 %result
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}
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define i64 @mul_i24_s64_divergent(i32 %a, i32 %b) {
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; GFX9-LABEL: mul_i24_s64_divergent:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mul_hi_i32_i24_e32 v2, v0, v1
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; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1
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; GFX9-NEXT: v_mov_b32_e32 v1, v2
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: mul_i24_s64_divergent:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mul_i32_i24_e32 v2, v0, v1
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; GFX11-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX11-NEXT: v_mov_b32_e32 v0, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%result = call i64 @llvm.amdgcn.mul.i24.i64(i32 %a, i32 %b)
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ret i64 %result
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}
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define amdgpu_ps i64 @mul_i24_s64_uniform(i32 inreg %a, i32 inreg %b) {
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; GFX9-LABEL: mul_i24_s64_uniform:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v0, s1
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; GFX9-NEXT: v_mul_hi_i32_i24_e32 v1, s0, v0
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; GFX9-NEXT: v_mul_i32_i24_e32 v0, s0, v0
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; GFX9-NEXT: v_readfirstlane_b32 s0, v0
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; GFX9-NEXT: v_readfirstlane_b32 s1, v1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mul_i24_s64_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mul_i32_i24_e64 v0, s0, s1
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; GFX11-NEXT: v_mul_hi_i32_i24_e64 v1, s0, s1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v0
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; GFX11-NEXT: v_readfirstlane_b32 s1, v1
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; GFX11-NEXT: ; return to shader part epilog
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%result = call i64 @llvm.amdgcn.mul.i24.i64(i32 %a, i32 %b)
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ret i64 %result
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}
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define i32 @mulhi_u24_s32_divergent(i32 %a, i32 %b) {
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; GFX9-LABEL: mulhi_u24_s32_divergent:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mul_hi_u32_u24_e32 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: mulhi_u24_s32_divergent:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mul_hi_u32_u24_e32 v0, v0, v1
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%result = call i32 @llvm.amdgcn.mulhi.u24(i32 %a, i32 %b)
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ret i32 %result
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}
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define amdgpu_ps i32 @mulhi_u24_s32_uniform(i32 inreg %a, i32 inreg %b) {
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; GFX9-LABEL: mulhi_u24_s32_uniform:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v0, s1
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; GFX9-NEXT: v_mul_hi_u32_u24_e32 v0, s0, v0
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; GFX9-NEXT: v_readfirstlane_b32 s0, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mulhi_u24_s32_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mul_hi_u32_u24_e64 v0, s0, s1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v0
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; GFX11-NEXT: ; return to shader part epilog
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%result = call i32 @llvm.amdgcn.mulhi.u24(i32 %a, i32 %b)
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ret i32 %result
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}
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define i32 @mulhi_i24_s32_divergent(i32 %a, i32 %b) {
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; GFX9-LABEL: mulhi_i24_s32_divergent:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mul_hi_i32_i24_e32 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: mulhi_i24_s32_divergent:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mul_hi_i32_i24_e32 v0, v0, v1
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%result = call i32 @llvm.amdgcn.mulhi.i24(i32 %a, i32 %b)
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ret i32 %result
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}
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define amdgpu_ps i32 @mulhi_i24_s32_uniform(i32 inreg %a, i32 inreg %b) {
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; GFX9-LABEL: mulhi_i24_s32_uniform:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v0, s1
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; GFX9-NEXT: v_mul_hi_i32_i24_e32 v0, s0, v0
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; GFX9-NEXT: v_readfirstlane_b32 s0, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mulhi_i24_s32_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mul_hi_i32_i24_e64 v0, s0, s1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v0
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; GFX11-NEXT: ; return to shader part epilog
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%result = call i32 @llvm.amdgcn.mulhi.i24(i32 %a, i32 %b)
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ret i32 %result
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}
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declare i32 @llvm.amdgcn.mul.u24.i32(i32, i32)
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declare i64 @llvm.amdgcn.mul.u24.i64(i32, i32)
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declare i32 @llvm.amdgcn.mul.i24.i32(i32, i32)
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declare i64 @llvm.amdgcn.mul.i24.i64(i32, i32)
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declare i32 @llvm.amdgcn.mulhi.u24(i32, i32)
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declare i32 @llvm.amdgcn.mulhi.i24(i32, i32)
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