derek.holloway
7502bf64a4
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201 lines
7.6 KiB
LLVM
201 lines
7.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,CI %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,VI %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
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define double @v_trig_preop_f64(double %a, i32 %b) {
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; GCN-LABEL: v_trig_preop_f64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_trig_preop_f64 v[0:1], v[0:1], v2
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10PLUS-LABEL: v_trig_preop_f64:
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; GFX10PLUS: ; %bb.0:
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; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10PLUS-NEXT: v_trig_preop_f64 v[0:1], v[0:1], v2
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; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
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%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b)
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ret double %result
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}
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define double @v_trig_preop_f64_imm(double %a, i32 %b) {
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; GCN-LABEL: v_trig_preop_f64_imm:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_trig_preop_f64 v[0:1], v[0:1], 7
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10PLUS-LABEL: v_trig_preop_f64_imm:
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; GFX10PLUS: ; %bb.0:
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; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10PLUS-NEXT: v_trig_preop_f64 v[0:1], v[0:1], 7
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; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
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%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7)
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ret double %result
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}
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define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) {
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; CI-LABEL: s_trig_preop_f64:
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; CI: ; %bb.0:
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; CI-NEXT: s_load_dword s2, s[8:9], 0x2
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; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; CI-NEXT: s_add_i32 s12, s12, s17
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; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
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; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
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; CI-NEXT: s_waitcnt lgkmcnt(0)
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; CI-NEXT: v_mov_b32_e32 v0, s2
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; CI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0
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; CI-NEXT: s_add_u32 s0, s0, 4
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; CI-NEXT: s_addc_u32 s1, s1, 0
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; CI-NEXT: v_mov_b32_e32 v3, s1
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; CI-NEXT: v_mov_b32_e32 v2, s0
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; CI-NEXT: flat_store_dword v[0:1], v0
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; CI-NEXT: s_waitcnt vmcnt(0)
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; CI-NEXT: flat_store_dword v[2:3], v1
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; CI-NEXT: s_waitcnt vmcnt(0)
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; CI-NEXT: s_endpgm
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;
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; VI-LABEL: s_trig_preop_f64:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dword s2, s[8:9], 0x8
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; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; VI-NEXT: s_add_i32 s12, s12, s17
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; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
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; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v0, s2
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; VI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0
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; VI-NEXT: s_add_u32 s0, s0, 4
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; VI-NEXT: s_addc_u32 s1, s1, 0
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; VI-NEXT: v_mov_b32_e32 v3, s1
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; VI-NEXT: v_mov_b32_e32 v2, s0
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; VI-NEXT: flat_store_dword v[0:1], v0
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: flat_store_dword v[2:3], v1
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: s_trig_preop_f64:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, s2
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; GFX9-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0
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; GFX9-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: s_trig_preop_f64:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_add_u32 s12, s12, s17
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; GFX10-NEXT: s_addc_u32 s13, s13, 0
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; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
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; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
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; GFX10-NEXT: s_clause 0x1
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; GFX10-NEXT: s_load_dword s2, s[8:9], 0x8
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_trig_preop_f64 v[0:1], s[0:1], s2
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; GFX10-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: s_trig_preop_f64:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_trig_preop_f64 v[0:1], s[0:1], s2
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; GFX11-NEXT: flat_store_b64 v[0:1], v[0:1] dlc
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; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-NEXT: s_endpgm
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%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b)
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store volatile double %result, ptr poison
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ret void
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}
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define amdgpu_kernel void @s_trig_preop_f64_imm(double %a, i32 %b) {
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; CI-LABEL: s_trig_preop_f64_imm:
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; CI: ; %bb.0:
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; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; CI-NEXT: s_add_i32 s12, s12, s17
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; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
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; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
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; CI-NEXT: s_waitcnt lgkmcnt(0)
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; CI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7
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; CI-NEXT: s_add_u32 s0, s0, 4
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; CI-NEXT: s_addc_u32 s1, s1, 0
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; CI-NEXT: v_mov_b32_e32 v3, s1
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; CI-NEXT: v_mov_b32_e32 v2, s0
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; CI-NEXT: flat_store_dword v[0:1], v0
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; CI-NEXT: s_waitcnt vmcnt(0)
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; CI-NEXT: flat_store_dword v[2:3], v1
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; CI-NEXT: s_waitcnt vmcnt(0)
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; CI-NEXT: s_endpgm
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;
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; VI-LABEL: s_trig_preop_f64_imm:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; VI-NEXT: s_add_i32 s12, s12, s17
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; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
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; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7
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; VI-NEXT: s_add_u32 s0, s0, 4
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; VI-NEXT: s_addc_u32 s1, s1, 0
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; VI-NEXT: v_mov_b32_e32 v3, s1
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; VI-NEXT: v_mov_b32_e32 v2, s0
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; VI-NEXT: flat_store_dword v[0:1], v0
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: flat_store_dword v[2:3], v1
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: s_trig_preop_f64_imm:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7
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; GFX9-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: s_trig_preop_f64_imm:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_add_u32 s12, s12, s17
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; GFX10-NEXT: s_addc_u32 s13, s13, 0
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; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
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; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7
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; GFX10-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: s_trig_preop_f64_imm:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7
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; GFX11-NEXT: flat_store_b64 v[0:1], v[0:1] dlc
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; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-NEXT: s_endpgm
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%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7)
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store volatile double %result, ptr poison
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ret void
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}
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declare double @llvm.amdgcn.trig.preop.f64(double, i32) #0
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attributes #0 = { nounwind readnone speculatable }
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