derek.holloway
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109 lines
4.2 KiB
LLVM
109 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck --check-prefix=GFX906 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck --check-prefix=GFX10PLUS %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck --check-prefix=GFX10PLUS %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefix=GFX10PLUS %s
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define i32 @v_udot8(i32 %a, i32 %b, i32 %c) {
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; GFX906-LABEL: v_udot8:
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; GFX906: ; %bb.0:
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; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
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; GFX906-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10PLUS-LABEL: v_udot8:
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; GFX10PLUS: ; %bb.0:
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; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
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; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
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%r = call i32 @llvm.amdgcn.udot8(i32 %a, i32 %b, i32 %c, i1 false)
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ret i32 %r
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}
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define i32 @v_udot8_clamp(i32 %a, i32 %b, i32 %c) {
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; GFX906-LABEL: v_udot8_clamp:
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; GFX906: ; %bb.0:
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; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2 clamp
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; GFX906-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10PLUS-LABEL: v_udot8_clamp:
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; GFX10PLUS: ; %bb.0:
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; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2 clamp
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; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
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%r = call i32 @llvm.amdgcn.udot8(i32 %a, i32 %b, i32 %c, i1 true)
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ret i32 %r
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}
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; FIXME: Fix argument do not let these casts expand
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; define i32 @v_udot8_cast_v8i4(<8 x i4> %a, <8 x i4> %b, i32 %c) {
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; %a.cast = bitcast <8 x i4> %a to i32
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; %b.cast = bitcast <8 x i4> %b to i32
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; %r = call i32 @llvm.amdgcn.udot8(i32 %a.cast, i32 %b.cast, i32 %c, i1 false)
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; ret i32 %r
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; }
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define i32 @v_udot8_fnegf32_a(float %a, i32 %b, i32 %c) {
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; GFX906-LABEL: v_udot8_fnegf32_a:
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; GFX906: ; %bb.0:
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; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX906-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
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; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
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; GFX906-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10PLUS-LABEL: v_udot8_fnegf32_a:
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; GFX10PLUS: ; %bb.0:
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; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
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; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
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; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
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%neg.a = fneg float %a
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%cast.neg.a = bitcast float %neg.a to i32
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%r = call i32 @llvm.amdgcn.udot8(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
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ret i32 %r
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}
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define i32 @v_udot8_fnegv2f16_a(<2 x half> %a, i32 %b, i32 %c) {
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; GFX906-LABEL: v_udot8_fnegv2f16_a:
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; GFX906: ; %bb.0:
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; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX906-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
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; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
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; GFX906-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10PLUS-LABEL: v_udot8_fnegv2f16_a:
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; GFX10PLUS: ; %bb.0:
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; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
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; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
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; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
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%neg.a = fneg <2 x half> %a
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%cast.neg.a = bitcast <2 x half> %neg.a to i32
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%r = call i32 @llvm.amdgcn.udot8(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
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ret i32 %r
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}
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define amdgpu_ps i32 @v_udot8_s_s_s(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
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; GFX906-LABEL: v_udot8_s_s_s:
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; GFX906: ; %bb.0:
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; GFX906-NEXT: v_mov_b32_e32 v0, s1
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; GFX906-NEXT: v_mov_b32_e32 v1, s2
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; GFX906-NEXT: v_dot8_u32_u4 v0, s0, v0, v1
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; GFX906-NEXT: v_readfirstlane_b32 s0, v0
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; GFX906-NEXT: ; return to shader part epilog
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;
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; GFX10PLUS-LABEL: v_udot8_s_s_s:
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; GFX10PLUS: ; %bb.0:
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; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s2
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; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, s0, s1, v0
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; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
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; GFX10PLUS-NEXT: ; return to shader part epilog
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%r = call i32 @llvm.amdgcn.udot8(i32 %a, i32 %b, i32 %c, i1 false)
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ret i32 %r
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}
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declare i32 @llvm.amdgcn.udot8(i32, i32, i32, i1 immarg) #0
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attributes #0 = { nounwind readnone speculatable }
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