derek.holloway
7502bf64a4
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232 lines
8.4 KiB
LLVM
232 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GFX11 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX12 %s
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define amdgpu_ps void @sextload_P1_i8_gfx12(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {
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; GFX11-LABEL: sextload_P1_i8_gfx12:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: global_load_i8 v2, v2, s[0:1]
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v2
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; GFX11-NEXT: s_add_i32 s0, s0, s0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_mov_b32_e32 v2, s0
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; GFX11-NEXT: global_store_b32 v[0:1], v2, off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: sextload_P1_i8_gfx12:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_i8 s0, s[0:1], 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_add_co_i32 s0, s0, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v2, s0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_endpgm
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%a = load i8, ptr addrspace(1) %ptra
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%a32 = sext i8 %a to i32
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%res = add i32 %a32, %a32
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store i32 %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @sextload_P1_i8_align4_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {
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; GFX11-LABEL: sextload_P1_i8_align4_gfx11:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_sext_i32_i8 s0, s0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX11-NEXT: s_add_i32 s0, s0, s0
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; GFX11-NEXT: v_mov_b32_e32 v2, s0
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; GFX11-NEXT: global_store_b32 v[0:1], v2, off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: sextload_P1_i8_align4_gfx11:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_i8 s0, s[0:1], 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_add_co_i32 s0, s0, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v2, s0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_endpgm
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%a = load i8, ptr addrspace(1) %ptra, align 4
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%a32 = sext i8 %a to i32
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%res = add i32 %a32, %a32
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store i32 %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @sextload_P1_i16_gfx12(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {
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; GFX11-LABEL: sextload_P1_i16_gfx12:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: global_load_i16 v2, v2, s[0:1]
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v2
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; GFX11-NEXT: s_add_i32 s0, s0, s0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_mov_b32_e32 v2, s0
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; GFX11-NEXT: global_store_b32 v[0:1], v2, off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: sextload_P1_i16_gfx12:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_i16 s0, s[0:1], 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_add_co_i32 s0, s0, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v2, s0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_endpgm
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%a = load i16, ptr addrspace(1) %ptra
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%a32 = sext i16 %a to i32
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%res = add i32 %a32, %a32
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store i32 %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @sextload_P1_i16_align4_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {
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; GFX11-LABEL: sextload_P1_i16_align4_gfx11:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_sext_i32_i16 s0, s0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX11-NEXT: s_add_i32 s0, s0, s0
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; GFX11-NEXT: v_mov_b32_e32 v2, s0
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; GFX11-NEXT: global_store_b32 v[0:1], v2, off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: sextload_P1_i16_align4_gfx11:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_i16 s0, s[0:1], 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_add_co_i32 s0, s0, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v2, s0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_endpgm
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%a = load i16, ptr addrspace(1) %ptra, align 4
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%a32 = sext i16 %a to i32
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%res = add i32 %a32, %a32
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store i32 %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @zextload_P1_i8_gfx12(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {
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; GFX11-LABEL: zextload_P1_i8_gfx12:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: global_load_u8 v2, v2, s[0:1]
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v2
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; GFX11-NEXT: s_add_i32 s0, s0, s0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_mov_b32_e32 v2, s0
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; GFX11-NEXT: global_store_b32 v[0:1], v2, off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: zextload_P1_i8_gfx12:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_add_co_i32 s0, s0, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v2, s0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_endpgm
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%a = load i8, ptr addrspace(1) %ptra
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%a32 = zext i8 %a to i32
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%res = add i32 %a32, %a32
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store i32 %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @zextload_P1_i8_align4_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {
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; GFX11-LABEL: zextload_P1_i8_align4_gfx11:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_and_b32 s0, s0, 0xff
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX11-NEXT: s_add_i32 s0, s0, s0
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; GFX11-NEXT: v_mov_b32_e32 v2, s0
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; GFX11-NEXT: global_store_b32 v[0:1], v2, off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: zextload_P1_i8_align4_gfx11:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_add_co_i32 s0, s0, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v2, s0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_endpgm
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%a = load i8, ptr addrspace(1) %ptra, align 4
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%a32 = zext i8 %a to i32
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%res = add i32 %a32, %a32
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store i32 %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @zextload_P1_i16_gfx12(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {
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; GFX11-LABEL: zextload_P1_i16_gfx12:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: global_load_u16 v2, v2, s[0:1]
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v2
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; GFX11-NEXT: s_add_i32 s0, s0, s0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_mov_b32_e32 v2, s0
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; GFX11-NEXT: global_store_b32 v[0:1], v2, off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: zextload_P1_i16_gfx12:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_add_co_i32 s0, s0, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v2, s0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_endpgm
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%a = load i16, ptr addrspace(1) %ptra
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%a32 = zext i16 %a to i32
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%res = add i32 %a32, %a32
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store i32 %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @zextload_P1_i16_align4_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {
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; GFX11-LABEL: zextload_P1_i16_align4_gfx11:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX11-NEXT: s_add_i32 s0, s0, s0
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; GFX11-NEXT: v_mov_b32_e32 v2, s0
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; GFX11-NEXT: global_store_b32 v[0:1], v2, off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: zextload_P1_i16_align4_gfx11:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_add_co_i32 s0, s0, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v2, s0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_endpgm
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%a = load i16, ptr addrspace(1) %ptra, align 4
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%a32 = zext i16 %a to i32
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%res = add i32 %a32, %a32
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store i32 %res, ptr addrspace(1) %out
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ret void
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}
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