derek.holloway
7502bf64a4
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157 lines
4.9 KiB
YAML
157 lines
4.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck --check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck --check-prefix=GCN %s
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---
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name: bfe_sext_inreg_ashr_s32
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $vgpr0
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; GCN-LABEL: name: bfe_sext_inreg_ashr_s32
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; GCN-NEXT: [[SBFX:%[0-9]+]]:_(s32) = G_SBFX [[COPY]], [[C]](s32), [[C1]]
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; GCN-NEXT: $vgpr0 = COPY [[SBFX]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CONSTANT i32 4
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%2:_(s32) = G_ASHR %0, %1(s32)
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%3:_(s32) = COPY %2(s32)
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%4:_(s32) = G_SEXT_INREG %3, 16
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$vgpr0 = COPY %4(s32)
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...
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---
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name: bfe_sext_inreg_lshr_s32
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $vgpr0
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; GCN-LABEL: name: bfe_sext_inreg_lshr_s32
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; GCN-NEXT: [[SBFX:%[0-9]+]]:_(s32) = G_SBFX [[COPY]], [[C]](s32), [[C1]]
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; GCN-NEXT: $vgpr0 = COPY [[SBFX]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CONSTANT i32 4
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%2:_(s32) = G_LSHR %0, %1(s32)
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%3:_(s32) = COPY %2(s32)
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%4:_(s32) = G_SEXT_INREG %3, 16
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$vgpr0 = COPY %4(s32)
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...
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---
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name: bfe_sext_inreg_ashr_s64
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: bfe_sext_inreg_ashr_s64
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; GCN: liveins: $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; GCN-NEXT: [[SBFX:%[0-9]+]]:_(s64) = G_SBFX [[COPY]], [[C]](s32), [[C1]]
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; GCN-NEXT: $vgpr0_vgpr1 = COPY [[SBFX]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 4
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%2:_(s64) = G_ASHR %0, %1(s32)
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%3:_(s64) = COPY %2(s64)
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%4:_(s64) = G_SEXT_INREG %3, 16
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$vgpr0_vgpr1 = COPY %4(s64)
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...
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---
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name: toobig_sext_inreg_ashr_s32
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $vgpr0
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; GCN-LABEL: name: toobig_sext_inreg_ashr_s32
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; GCN-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
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; GCN-NEXT: $vgpr0 = COPY [[ASHR]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CONSTANT i32 16
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%2:_(s32) = G_ASHR %0, %1(s32)
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%3:_(s32) = COPY %2(s32)
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%4:_(s32) = G_SEXT_INREG %3, 20
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$vgpr0 = COPY %4(s32)
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...
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---
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name: toobig_sext_inreg_ashr_s64
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: toobig_sext_inreg_ashr_s64
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; GCN: liveins: $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; GCN-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
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; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; GCN-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32)
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; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR]](s32)
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; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[MV]], 32
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; GCN-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 40
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%2:_(s64) = G_ASHR %0, %1(s32)
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%3:_(s64) = COPY %2(s64)
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%4:_(s64) = G_SEXT_INREG %3, 32
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$vgpr0_vgpr1 = COPY %4(s64)
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...
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---
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name: var_sext_inreg_ashr_s32
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: var_sext_inreg_ashr_s32
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; GCN: liveins: $vgpr0, $vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; GCN-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
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; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ASHR]], 10
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; GCN-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = G_ASHR %0, %1(s32)
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%3:_(s32) = COPY %2(s32)
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%4:_(s32) = G_SEXT_INREG %3, 10
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$vgpr0 = COPY %4(s32)
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...
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