derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
111 lines
4.7 KiB
YAML
111 lines
4.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
|
|
|
|
--- |
|
|
define amdgpu_ps void @exp_s(float inreg %v0, float inreg %v1, float inreg %v2, float inreg %v3) {
|
|
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %v0, float %v1, float %v2, float %v3, i1 false, i1 false)
|
|
ret void
|
|
}
|
|
define amdgpu_ps void @exp_v(float %v0, float %v1, float %v2, float %v3) {
|
|
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %v0, float %v1, float %v2, float %v3, i1 false, i1 false)
|
|
ret void
|
|
}
|
|
define amdgpu_ps void @exp_row_s(i32 inreg %row, float inreg %val) {
|
|
call void @llvm.amdgcn.exp.row.f32(i32 12, i32 1, float %val, float %val, float %val, float %val, i1 true, i32 %row)
|
|
ret void
|
|
}
|
|
define amdgpu_ps void @exp_row_v(float %val, i32 %row) {
|
|
call void @llvm.amdgcn.exp.row.f32(i32 12, i32 1, float %val, float %val, float %val, float %val, i1 true, i32 %row)
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1)
|
|
declare void @llvm.amdgcn.exp.row.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i32)
|
|
...
|
|
|
|
---
|
|
name: exp_s
|
|
legalized: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
|
|
; CHECK-LABEL: name: exp_s
|
|
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
|
|
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
|
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
|
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
|
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY3]](s32)
|
|
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), 0, 0
|
|
%0:_(s32) = COPY $sgpr0
|
|
%1:_(s32) = COPY $sgpr1
|
|
%2:_(s32) = COPY $sgpr2
|
|
%3:_(s32) = COPY $sgpr3
|
|
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, %0(s32), %1(s32), %2(s32), %3(s32), 0, 0
|
|
...
|
|
---
|
|
name: exp_v
|
|
legalized: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
|
|
; CHECK-LABEL: name: exp_v
|
|
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
|
|
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), 0, 0
|
|
%0:_(s32) = COPY $vgpr0
|
|
%1:_(s32) = COPY $vgpr1
|
|
%2:_(s32) = COPY $vgpr2
|
|
%3:_(s32) = COPY $vgpr3
|
|
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, %0(s32), %1(s32), %2(s32), %3(s32), 0, 0
|
|
...
|
|
---
|
|
name: exp_row_s
|
|
legalized: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0, $sgpr1
|
|
; CHECK-LABEL: name: exp_row_s
|
|
; CHECK: liveins: $sgpr0, $sgpr1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
|
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
|
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
|
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.row), 12, 1, [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), -1, [[COPY]](s32)
|
|
%0:_(s32) = COPY $sgpr0
|
|
%1:_(s32) = COPY $sgpr1
|
|
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.row), 12, 1, %1(s32), %1(s32), %1(s32), %1(s32), -1, %0(s32)
|
|
...
|
|
---
|
|
name: exp_row_v
|
|
legalized: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0, $vgpr1
|
|
; CHECK-LABEL: name: exp_row_v
|
|
; CHECK: liveins: $vgpr0, $vgpr1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
|
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
|
|
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.row), 12, 1, [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), -1, [[INTRINSIC_CONVERGENT]](s32)
|
|
%0:_(s32) = COPY $vgpr0
|
|
%1:_(s32) = COPY $vgpr1
|
|
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.row), 12, 1, %0(s32), %0(s32), %0(s32), %0(s32), -1, %1(s32)
|
|
...
|