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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
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Flatten subprojects into a single base monorepo
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
---
name: amdgpu_atomic_cmpxchg_global_i32_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
; CHECK-LABEL: name: amdgpu_atomic_cmpxchg_global_i32_ss
; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(<2 x s32>) = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:vgpr(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY3]](p1), [[COPY4]] :: (load store seq_cst (s32), addrspace 1)
%0:_(p1) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = COPY $sgpr3
%3:_(<2 x s32>) = G_BUILD_VECTOR %2, %1
%4:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG %0, %3 :: (load store seq_cst (s32), addrspace 1)
...
---
name: amdgpu_atomic_cmpxchg_global_i64_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5
; CHECK-LABEL: name: amdgpu_atomic_cmpxchg_global_i64_ss
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
; CHECK-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
; CHECK-NEXT: [[MV2:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV1]](s64)
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(p1) = COPY [[MV]](p1)
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(<2 x s64>) = COPY [[BUILD_VECTOR]](<2 x s64>)
; CHECK-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:vgpr(s64) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY6]](p1), [[COPY7]] :: (load store seq_cst (s64), addrspace 1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(p1) = G_MERGE_VALUES %0, %1
%3:_(s32) = COPY $sgpr2
%4:_(s32) = COPY $sgpr3
%5:_(s64) = G_MERGE_VALUES %3, %4
%6:_(s32) = COPY $sgpr4
%7:_(s32) = COPY $sgpr5
%8:_(s64) = G_MERGE_VALUES %6, %7
%9:_(<2 x s64>) = G_BUILD_VECTOR %8, %5
%10:_(s64) = G_AMDGPU_ATOMIC_CMPXCHG %2, %9 :: (load store seq_cst (s64), addrspace 1)
...
---
name: amdgpu_atomic_cmpxchg_flat_i32_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
; CHECK-LABEL: name: amdgpu_atomic_cmpxchg_flat_i32_ss
; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(<2 x s32>) = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:vgpr(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY3]](p0), [[COPY4]] :: (load store seq_cst (s32))
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = COPY $sgpr3
%3:_(<2 x s32>) = G_BUILD_VECTOR %2, %1
%4:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG %0, %3 :: (load store seq_cst (s32), addrspace 0)
...
---
name: amdgpu_atomic_cmpxchg_flat_i64_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5
; CHECK-LABEL: name: amdgpu_atomic_cmpxchg_flat_i64_ss
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
; CHECK-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
; CHECK-NEXT: [[MV2:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV1]](s64)
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(p0) = COPY [[MV]](p0)
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(<2 x s64>) = COPY [[BUILD_VECTOR]](<2 x s64>)
; CHECK-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:vgpr(s64) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY6]](p0), [[COPY7]] :: (load store seq_cst (s64))
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(p0) = G_MERGE_VALUES %0, %1
%3:_(s32) = COPY $sgpr2
%4:_(s32) = COPY $sgpr3
%5:_(s64) = G_MERGE_VALUES %3, %4
%6:_(s32) = COPY $sgpr4
%7:_(s32) = COPY $sgpr5
%8:_(s64) = G_MERGE_VALUES %6, %7
%9:_(<2 x s64>) = G_BUILD_VECTOR %8, %5
%10:_(s64) = G_AMDGPU_ATOMIC_CMPXCHG %2, %9 :: (load store seq_cst (s64), addrspace 0)
...
---
name: atomic_cmpxchg_region_i32_sss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; CHECK-LABEL: name: atomic_cmpxchg_region_i32_sss
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p2) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p2) = COPY [[COPY]](p2)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
; CHECK-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:vgpr(s32) = G_ATOMIC_CMPXCHG [[COPY3]](p2), [[COPY4]], [[COPY5]] :: (load store seq_cst (s32), addrspace 2)
%0:_(p2) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s32), addrspace 2)
...
---
name: atomic_cmpxchg_region_i64_sss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr2, $sgpr3, $sgpr4, $sgpr5
; CHECK-LABEL: name: atomic_cmpxchg_region_i64_sss
; CHECK: liveins: $sgpr0, $sgpr2, $sgpr3, $sgpr4, $sgpr5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p2) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
; CHECK-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(p2) = COPY [[COPY]](p2)
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s64) = COPY [[MV]](s64)
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s64) = COPY [[MV1]](s64)
; CHECK-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:vgpr(s64) = G_ATOMIC_CMPXCHG [[COPY5]](p2), [[COPY6]], [[COPY7]] :: (load store seq_cst (s64), addrspace 2)
%0:_(p2) = COPY $sgpr0
%1:_(s32) = COPY $sgpr2
%2:_(s32) = COPY $sgpr3
%3:_(s64) = G_MERGE_VALUES %1, %2
%4:_(s32) = COPY $sgpr4
%5:_(s32) = COPY $sgpr5
%6:_(s64) = G_MERGE_VALUES %4, %5
%7:_(s64) = G_ATOMIC_CMPXCHG %0, %3, %6 :: (load store seq_cst (s64), addrspace 2)
...
---
name: atomic_cmpxchg_local_i32_sss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; CHECK-LABEL: name: atomic_cmpxchg_local_i32_sss
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
; CHECK-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:vgpr(s32) = G_ATOMIC_CMPXCHG [[COPY3]](p3), [[COPY4]], [[COPY5]] :: (load store seq_cst (s32), addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s32), addrspace 3)
...
---
name: atomic_cmpxchg_local_i64_sss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr2, $sgpr3, $sgpr4, $sgpr5
; CHECK-LABEL: name: atomic_cmpxchg_local_i64_sss
; CHECK: liveins: $sgpr0, $sgpr2, $sgpr3, $sgpr4, $sgpr5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
; CHECK-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s64) = COPY [[MV]](s64)
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s64) = COPY [[MV1]](s64)
; CHECK-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:vgpr(s64) = G_ATOMIC_CMPXCHG [[COPY5]](p3), [[COPY6]], [[COPY7]] :: (load store seq_cst (s64), addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = COPY $sgpr2
%2:_(s32) = COPY $sgpr3
%3:_(s64) = G_MERGE_VALUES %1, %2
%4:_(s32) = COPY $sgpr4
%5:_(s32) = COPY $sgpr5
%6:_(s64) = G_MERGE_VALUES %4, %5
%7:_(s64) = G_ATOMIC_CMPXCHG %0, %3, %6 :: (load store seq_cst (s64), addrspace 3)
...
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