derek.holloway
7502bf64a4
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217 lines
6.3 KiB
YAML
217 lines
6.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
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---
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name: brcond_vcc_cond
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legalized: true
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body: |
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; CHECK-LABEL: name: brcond_vcc_cond
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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bb.0.entry:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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G_BRCOND %2, %bb.1
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bb.1:
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...
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---
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name: brcond_scc_cond
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legalized: true
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body: |
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; CHECK-LABEL: name: brcond_scc_cond
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP]], [[C]]
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; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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bb.0.entry:
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successors: %bb.1
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liveins: $sgpr0, $sgpr1
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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G_BRCOND %2, %bb.1
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bb.1:
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...
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---
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name: brcond_sgpr_cond
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legalized: true
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body: |
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; CHECK-LABEL: name: brcond_sgpr_cond
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $sgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[C]]
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; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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bb.0.entry:
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successors: %bb.1
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liveins: $sgpr0
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%0:_(s32) = COPY $sgpr0
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%1:_(s1) = G_TRUNC %0
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G_BRCOND %1, %bb.1
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bb.1:
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...
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---
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name: brcond_vgpr_cond
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legalized: true
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body: |
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; CHECK-LABEL: name: brcond_vgpr_cond
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
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; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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bb.0.entry:
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successors: %bb.1
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liveins: $vgpr0
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%0:_(s32) = COPY $vgpr0
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%1:_(s1) = G_TRUNC %0
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G_BRCOND %1, %bb.1
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bb.1:
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...
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# The terminator that needs handling is the only instruction in the
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# block.
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---
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name: empty_block_vgpr_brcond
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legalized: true
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body: |
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; CHECK-LABEL: name: empty_block_vgpr_brcond
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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bb.0.entry:
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successors: %bb.1
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liveins: $vgpr0
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%0:_(s32) = COPY $vgpr0
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%1:_(s1) = G_TRUNC %0
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bb.1:
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G_BRCOND %1, %bb.1
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bb.2:
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...
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# Make sure the first instruction in the block isn't skipped.
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---
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name: copy_first_inst_brcond
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legalized: true
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body: |
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; CHECK-LABEL: name: copy_first_inst_brcond
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
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; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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bb.0.entry:
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successors: %bb.1
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liveins: $vgpr0
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%0:_(s32) = COPY $vgpr0
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bb.1:
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%1:_(s1) = G_TRUNC %0
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G_BRCOND %1, %bb.1
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bb.2:
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...
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# Extra instruction separates brcond from the condition def
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---
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name: copy_middle_inst_brcond
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legalized: true
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body: |
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; CHECK-LABEL: name: copy_middle_inst_brcond
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
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; CHECK-NEXT: S_NOP 0
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; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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bb.0.entry:
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successors: %bb.1
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liveins: $vgpr0
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%0:_(s32) = COPY $vgpr0
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bb.1:
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%1:_(s1) = G_TRUNC %0
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S_NOP 0
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G_BRCOND %1, %bb.1
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bb.2:
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...
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