derek.holloway
7502bf64a4
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338 lines
11 KiB
YAML
338 lines
11 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX1150 %s
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---
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name: fadd_f32
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX1150-LABEL: name: fadd_f32
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; GFX1150: liveins: $sgpr0, $sgpr1
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; GFX1150-NEXT: [[FADD:%[0-9]+]]:sgpr(s32) = G_FADD [[COPY]], [[COPY1]]
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = G_FADD %0, %1
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...
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---
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name: fptosi_f32_to_i32
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX1150-LABEL: name: fptosi_f32_to_i32
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; GFX1150: liveins: $sgpr0
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[FPTOSI:%[0-9]+]]:sgpr(s32) = G_FPTOSI [[COPY]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = G_FPTOSI %0(s32)
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...
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---
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name: fptoui_f32_to_u32
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX1150-LABEL: name: fptoui_f32_to_u32
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; GFX1150: liveins: $sgpr0
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[FPTOUI:%[0-9]+]]:sgpr(s32) = G_FPTOUI [[COPY]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = G_FPTOUI %0(s32)
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...
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---
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name: fptosi_sat_f32_to_i32
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX1150-LABEL: name: fptosi_sat_f32_to_i32
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; GFX1150: liveins: $sgpr0
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[FPTOSI_SAT:%[0-9]+]]:sgpr(s32) = G_FPTOSI_SAT [[COPY]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = G_FPTOSI_SAT %0(s32)
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...
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---
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name: fptoui_sat_f32_to_u32
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX1150-LABEL: name: fptoui_sat_f32_to_u32
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; GFX1150: liveins: $sgpr0
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[FPTOUI_SAT:%[0-9]+]]:sgpr(s32) = G_FPTOUI_SAT [[COPY]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = G_FPTOUI_SAT %0(s32)
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...
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---
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name: sitofp_i32_to_f32
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX1150-LABEL: name: sitofp_i32_to_f32
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; GFX1150: liveins: $sgpr0
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[SITOFP:%[0-9]+]]:sgpr(s32) = G_SITOFP [[COPY]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = G_SITOFP %0(s32)
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...
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---
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name: uitofp_u32_to_f32
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX1150-LABEL: name: uitofp_u32_to_f32
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; GFX1150: liveins: $sgpr0
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[UITOFP:%[0-9]+]]:sgpr(s32) = G_UITOFP [[COPY]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = G_UITOFP %0(s32)
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...
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---
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name: fptrunc_f32_to_f16
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX1150-LABEL: name: fptrunc_f32_to_f16
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; GFX1150: liveins: $sgpr0
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[FPTRUNC:%[0-9]+]]:sgpr(s16) = G_FPTRUNC [[COPY]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s16) = G_FPTRUNC %0(s32)
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...
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---
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name: fpext_f16_to_f32
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX1150-LABEL: name: fpext_f16_to_f32
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; GFX1150: liveins: $sgpr0
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
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%1:_(s32) = COPY $sgpr0
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%0:_(s16) = G_TRUNC %1(s32)
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...
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# Tests below should not select scalar registers
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# TODO: G_UNMERGE_VALUES, G_AMDGPU_READANYLANE, G_MERGE_VALUES should be combined away.
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---
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name: fadd_f64
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; GFX1150-LABEL: name: fadd_f64
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; GFX1150: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
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; GFX1150-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
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; GFX1150-NEXT: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
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; GFX1150-NEXT: [[FADD:%[0-9]+]]:vgpr(s64) = G_FADD [[COPY2]], [[COPY3]]
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; GFX1150-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[FADD]](s64)
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; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV]]
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; GFX1150-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV1]]
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; GFX1150-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32)
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(s64) = COPY $sgpr2_sgpr3
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%2:_(s64) = G_FADD %0, %1
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...
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---
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name: fptosi_f64_to_i32
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX1150-LABEL: name: fptosi_f64_to_i32
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; GFX1150: liveins: $sgpr0, $sgpr1
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
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; GFX1150-NEXT: [[FPTOSI:%[0-9]+]]:vgpr(s32) = G_FPTOSI [[COPY1]](s64)
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; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[FPTOSI]]
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(s32) = G_FPTOSI %0(s64)
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...
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---
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name: fptoui_f16_to_u16
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX1150-LABEL: name: fptoui_f16_to_u16
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; GFX1150: liveins: $sgpr0
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
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; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
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; GFX1150-NEXT: [[FPTOUI:%[0-9]+]]:vgpr(s16) = G_FPTOUI [[COPY1]](s16)
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; GFX1150-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FPTOUI]](s16)
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; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[ANYEXT]]
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; GFX1150-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[AMDGPU_READANYLANE]](s32)
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%1:_(s32) = COPY $sgpr0
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s16) = G_FPTOUI %0(s16)
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...
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---
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name: fptosi_sat_f64_to_i32
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX1150-LABEL: name: fptosi_sat_f64_to_i32
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; GFX1150: liveins: $sgpr0, $sgpr1
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
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; GFX1150-NEXT: [[FPTOSI_SAT:%[0-9]+]]:vgpr(s32) = G_FPTOSI_SAT [[COPY1]](s64)
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; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[FPTOSI_SAT]]
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(s32) = G_FPTOSI_SAT %0(s64)
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...
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---
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name: fptoui_sat_f16_to_u16
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX1150-LABEL: name: fptoui_sat_f16_to_u16
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; GFX1150: liveins: $sgpr0
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
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; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
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; GFX1150-NEXT: [[FPTOUI_SAT:%[0-9]+]]:vgpr(s16) = G_FPTOUI_SAT [[COPY1]](s16)
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; GFX1150-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FPTOUI_SAT]](s16)
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; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[ANYEXT]]
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; GFX1150-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[AMDGPU_READANYLANE]](s32)
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%1:_(s32) = COPY $sgpr0
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s16) = G_FPTOUI_SAT %0(s16)
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...
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---
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name: sitofp_i32_to_f64
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX1150-LABEL: name: sitofp_i32_to_f64
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; GFX1150: liveins: $sgpr0
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
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; GFX1150-NEXT: [[SITOFP:%[0-9]+]]:vgpr(s64) = G_SITOFP [[COPY1]](s32)
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; GFX1150-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[SITOFP]](s64)
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; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV]]
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; GFX1150-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV1]]
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; GFX1150-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s64) = G_SITOFP %0(s32)
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...
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---
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name: uitofp_u16_to_f16
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX1150-LABEL: name: uitofp_u16_to_f16
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; GFX1150: liveins: $sgpr0
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GFX1150-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
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; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
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; GFX1150-NEXT: [[UITOFP:%[0-9]+]]:vgpr(s16) = G_UITOFP [[COPY1]](s16)
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; GFX1150-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[UITOFP]](s16)
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; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[ANYEXT]]
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; GFX1150-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[AMDGPU_READANYLANE]](s32)
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%1:_(s32) = COPY $sgpr0
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s16) = G_UITOFP %0(s16)
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...
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---
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name: fptrunc_f64_to_f32
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; GFX1150-LABEL: name: fptrunc_f64_to_f32
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; GFX1150: liveins: $sgpr0_sgpr1
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; GFX1150-NEXT: {{ $}}
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; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
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; GFX1150-NEXT: [[FPTRUNC:%[0-9]+]]:vgpr(s32) = G_FPTRUNC [[COPY1]](s64)
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; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[FPTRUNC]]
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(s32) = G_FPTRUNC %0(s64)
|
|
...
|
|
|
|
---
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|
name: fpext_f32_to_f64
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|
legalized: true
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|
body: |
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|
bb.0:
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|
liveins: $sgpr0
|
|
|
|
; GFX1150-LABEL: name: fpext_f32_to_f64
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|
; GFX1150: liveins: $sgpr0
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|
; GFX1150-NEXT: {{ $}}
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|
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
|
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
|
; GFX1150-NEXT: [[FPEXT:%[0-9]+]]:vgpr(s64) = G_FPEXT [[COPY1]](s32)
|
|
; GFX1150-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[FPEXT]](s64)
|
|
; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV]]
|
|
; GFX1150-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV1]]
|
|
; GFX1150-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32)
|
|
%0:_(s32) = COPY $sgpr0
|
|
%1:_(s64) = G_FPEXT %0(s32)
|
|
|
|
...
|