derek.holloway
7502bf64a4
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198 lines
7.4 KiB
LLVM
198 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250 %s
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define amdgpu_ps i64 @s_mul_u64_u32(i32 inreg %a, i32 inreg %b) {
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; SI-LABEL: s_mul_u64_u32:
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; SI: ; %bb.0:
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; SI-NEXT: v_mov_b32_e32 v0, s1
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; SI-NEXT: v_mul_hi_u32 v0, s0, v0
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; SI-NEXT: s_mul_i32 s0, s0, s1
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; SI-NEXT: v_readfirstlane_b32 s1, v0
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; SI-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: s_mul_u64_u32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_mul_i32 s2, s0, s1
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; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
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; GFX11-NEXT: s_mov_b32 s0, s2
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX12-LABEL: s_mul_u64_u32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_mov_b32 s2, s1
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; GFX12-NEXT: s_mov_b32 s1, 0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX12-NEXT: s_mov_b32 s3, s1
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; GFX12-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3]
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: s_mul_u64_u32:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_mov_b32 s2, s1
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; GFX1250-NEXT: s_mov_b32 s1, 0
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; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX1250-NEXT: s_mov_b32 s3, s1
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; GFX1250-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3]
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; GFX1250-NEXT: ; return to shader part epilog
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%ext_a = zext i32 %a to i64
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%ext_b = zext i32 %b to i64
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%result = mul i64 %ext_a, %ext_b
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ret i64 %result
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}
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define amdgpu_ps i64 @s_mul_i64_i32(i32 inreg %a, i32 inreg %b) {
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; SI-LABEL: s_mul_i64_i32:
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; SI: ; %bb.0:
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; SI-NEXT: v_mov_b32_e32 v0, s1
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; SI-NEXT: v_mul_hi_u32 v0, s0, v0
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; SI-NEXT: s_ashr_i32 s4, s1, 31
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; SI-NEXT: s_ashr_i32 s3, s0, 31
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; SI-NEXT: s_mul_i32 s2, s0, s1
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; SI-NEXT: v_readfirstlane_b32 s5, v0
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; SI-NEXT: s_mul_i32 s0, s0, s4
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; SI-NEXT: s_mul_i32 s3, s3, s1
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; SI-NEXT: s_add_i32 s0, s5, s0
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; SI-NEXT: s_add_i32 s1, s0, s3
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; SI-NEXT: s_mov_b32 s0, s2
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; SI-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: s_mul_i64_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_ashr_i32 s2, s1, 31
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; GFX11-NEXT: s_mul_hi_u32 s3, s0, s1
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; GFX11-NEXT: s_mul_i32 s2, s0, s2
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; GFX11-NEXT: s_ashr_i32 s4, s0, 31
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; GFX11-NEXT: s_add_i32 s2, s3, s2
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; GFX11-NEXT: s_mul_i32 s4, s4, s1
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; GFX11-NEXT: s_mul_i32 s0, s0, s1
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; GFX11-NEXT: s_add_i32 s1, s2, s4
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX12-LABEL: s_mul_i64_i32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_mov_b32 s2, s1
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; GFX12-NEXT: s_ashr_i32 s1, s0, 31
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; GFX12-NEXT: s_ashr_i32 s3, s2, 31
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3]
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: s_mul_i64_i32:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_mov_b32 s2, s1
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; GFX1250-NEXT: s_ashr_i32 s1, s0, 31
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; GFX1250-NEXT: s_ashr_i32 s3, s2, 31
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; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX1250-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3]
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; GFX1250-NEXT: ; return to shader part epilog
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%ext_a = sext i32 %a to i64
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%ext_b = sext i32 %b to i64
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%result = mul i64 %ext_a, %ext_b
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ret i64 %result
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}
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define i64 @v_mul_u64_u32(i32 %a, i32 %b) {
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; SI-LABEL: v_mul_u64_u32:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_mul_lo_u32 v2, v0, v1
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; SI-NEXT: v_mul_hi_u32 v1, v0, v1
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; SI-NEXT: v_mov_b32_e32 v0, v2
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_mul_u64_u32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, v1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v3, 0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_mul_u64_u32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, v1
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v2, v3, 0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1250-LABEL: v_mul_u64_u32:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, v1
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v2, v3, 0
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ext_a = zext i32 %a to i64
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%ext_b = zext i32 %b to i64
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%result = mul i64 %ext_a, %ext_b
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ret i64 %result
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}
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define i64 @v_mul_i64_i32(i32 %a, i32 %b) {
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; SI-LABEL: v_mul_i64_i32:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_ashrrev_i32_e32 v3, 31, v1
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; SI-NEXT: v_ashrrev_i32_e32 v2, 31, v0
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; SI-NEXT: v_mul_hi_u32 v4, v0, v1
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; SI-NEXT: v_mul_lo_u32 v3, v0, v3
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; SI-NEXT: v_mul_lo_u32 v0, v0, v1
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; SI-NEXT: v_mul_lo_u32 v1, v2, v1
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; SI-NEXT: v_add_i32_e32 v2, vcc, v4, v3
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; SI-NEXT: v_add_i32_e32 v1, vcc, v2, v1
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_mul_i64_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, v1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
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; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v3, 0
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; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v3
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; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, v2, v6, v[1:2]
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; GFX11-NEXT: v_ashrrev_i32_e32 v5, 31, v2
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v5, v3, v[4:5]
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_mul_i64_i32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, v1
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v2, v3, 0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1250-LABEL: v_mul_i64_i32:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, v1
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-NEXT: v_mad_nc_i64_i32 v[0:1], v2, v3, 0
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ext_a = sext i32 %a to i64
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%ext_b = sext i32 %b to i64
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%result = mul i64 %ext_a, %ext_b
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ret i64 %result
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}
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