derek.holloway
7502bf64a4
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95 lines
5.0 KiB
LLVM
95 lines
5.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -filetype=obj < %s | llvm-objdump -s -j .rodata - | FileCheck --check-prefix=OBJDUMP %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck --check-prefix=ASM %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -filetype=obj < %s | llvm-objdump -s -j .rodata - | FileCheck --check-prefix=GFX1250-OBJDUMP %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck --check-prefix=GFX1250-ASM %s
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; OBJDUMP: Contents of section .rodata:
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; OBJDUMP-NEXT: 0000 00000000 00000000 10010000 00000000 ................
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; OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000 ................
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; OBJDUMP-NEXT: 0020 00000000 00000000 00000000 00000000 ................
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; OBJDUMP-NOT: 0030 0000af00 94130000 1a000400 00000000 ................
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; OBJDUMP-NEXT: 0030 8000af00 98130000 1e000400 00000000 ................
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; ASM-LABEL: amdhsa_kernarg_preload_4_implicit_6:
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; ASM: .amdhsa_user_sgpr_count 12
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; ASM: .amdhsa_next_free_sgpr 12
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; ASM: ; TotalNumSgprs: 18
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; ASM: ; NumSGPRsForWavesPerEU: 18
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; Test that we include preloaded SGPRs in the GRANULATED_WAVEFRONT_SGPR_COUNT
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; feild that are not explicitly referenced in the kernel. This test has 6 implicit
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; user SPGRs enabled, 4 preloaded kernarg SGPRs, plus 6 extra SGPRs allocated
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; for flat scratch, ect. The total number of allocated SGPRs encoded in the
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; kernel descriptor should be 16. That's a 1 in the KD field since the granule
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; size is 8 and it's NumGranules - 1. The encoding for that looks like '40'.
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define amdgpu_kernel void @amdhsa_kernarg_preload_4_implicit_6(i128 inreg) { ret void }
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; OBJDUMP-NEXT: 0040 00000000 00000000 20010000 00000000 ........ .......
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; OBJDUMP-NEXT: 0050 00000000 00000000 00000000 00000000 ................
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; OBJDUMP-NEXT: 0060 00000000 00000000 00000000 00000000 ................
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; OBJDUMP-NEXT: 0070 4000af00 94000000 08000800 00000000 @...............
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; ASM-LABEL: amdhsa_kernarg_preload_8_implicit_2:
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; ASM: .amdhsa_user_sgpr_count 10
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; ASM: .amdhsa_next_free_sgpr 10
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; ASM: ; TotalNumSgprs: 16
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; ASM: ; NumSGPRsForWavesPerEU: 16
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; Only the kernarg_ptr is enabled so we should have 8 preload kernarg SGPRs, 2
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; implicit, and 6 extra.
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define amdgpu_kernel void @amdhsa_kernarg_preload_8_implicit_2(i256 inreg) #0 { ret void }
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; OBJDUMP-NEXT: 0080 00000000 00000000 08010000 00000000 ................
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; OBJDUMP-NEXT: 0090 00000000 00000000 00000000 00000000 ................
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; OBJDUMP-NEXT: 00a0 00000000 00000000 00000000 00000000 ................
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; OBJDUMP-NEXT: 00b0 4000af00 86000000 08000100 00000000 @...............
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; ASM-LABEL: amdhsa_kernarg_preload_1_implicit_2:
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; ASM: .amdhsa_user_sgpr_count 3
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; ASM: .amdhsa_next_free_sgpr 3
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; ASM: ; TotalNumSgprs: 9
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; ASM: ; NumSGPRsForWavesPerEU: 9
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; 1 preload, 2 implicit, 6 extra. Rounds up to 16 SGPRs in the KD.
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define amdgpu_kernel void @amdhsa_kernarg_preload_1_implicit_2(i32 inreg) #0 { ret void }
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; OBJDUMP-NEXT: 00c0 00000000 00000000 08010000 00000000 ................
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; OBJDUMP-NEXT: 00d0 00000000 00000000 00000000 00000000 ................
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; OBJDUMP-NEXT: 00e0 00000000 00000000 00000000 00000000 ................
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; OBJDUMP-NEXT: 00f0 0000af00 84000000 08000000 00000000 ................
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; ASM-LABEL: amdhsa_kernarg_preload_0_implicit_2:
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; ASM: .amdhsa_user_sgpr_count 2
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; ASM: .amdhsa_next_free_sgpr 0
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; ASM: ; TotalNumSgprs: 6
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; ASM: ; NumSGPRsForWavesPerEU: 6
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; 0 preload kernarg SGPRs, 2 implicit, 6 extra. Rounds up to 8 SGPRs in the KD.
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; Encoded like '00'.
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define amdgpu_kernel void @amdhsa_kernarg_preload_0_implicit_2(i32) #0 { ret void }
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; GFX1250-OBJDUMP: 0100 00000000 00000000 90010000 00000000 ................
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; GFX1250-OBJDUMP: 0110 00000000 00000000 00000000 00000000 ................
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; GFX1250-OBJDUMP: 0120 00000000 00000000 00000000 10000000 ................
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; GFX1250-OBJDUMP: 0130 00000fc0 c0130000 1e041800 00000000 ................
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; GFX1250-ASM: .sgpr_count: 32
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define amdgpu_kernel void @many__i32(
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i32 inreg %a0, i32 inreg %a1, i32 inreg %a2, i32 inreg %a3,
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i32 inreg %a4, i32 inreg %a5, i32 inreg %a6, i32 inreg %a7,
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i32 inreg %a8, i32 inreg %a9, i32 inreg %a10, i32 inreg %a11,
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i32 inreg %a12, i32 inreg %a13, i32 inreg %a14, i32 inreg %a15,
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i32 inreg %a16, i32 inreg %a17, i32 inreg %a18, i32 inreg %a19,
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i32 inreg %a20, i32 inreg %a21, i32 inreg %a22, i32 inreg %a23,
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i32 inreg %a24, i32 inreg %a25, i32 inreg %a26, i32 inreg %a27,
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i32 inreg %a28, i32 inreg %a29, i32 inreg %a30, i32 inreg %a31,
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i32 inreg %a32, i32 inreg %a33, i32 inreg %a34, i32 inreg %a35) {
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ret void
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}
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attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
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