derek.holloway
7502bf64a4
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198 lines
7.9 KiB
LLVM
198 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=OPT %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-barrier-signal-wait-latency=0 < %s | FileCheck --check-prefix=NOOPT %s
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; Tests for scheduling independent work between s_barrier_signal and s_barrier_wait
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; for latency hiding.
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; Independent work should be scheduled between signal/wait
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define amdgpu_kernel void @test_barrier_independent_valu(ptr addrspace(1) %out, i32 %size) #0 {
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; OPT-LABEL: test_barrier_independent_valu:
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; OPT: ; %bb.0: ; %entry
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; OPT-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
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; OPT-NEXT: v_and_b32_e32 v1, 0x3ff, v0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; OPT-NEXT: v_lshlrev_b32_e32 v2, 2, v1
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; OPT-NEXT: s_wait_kmcnt 0x0
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; OPT-NEXT: v_xad_u32 v0, v1, -1, s2
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; OPT-NEXT: global_store_b32 v2, v1, s[0:1]
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; OPT-NEXT: s_barrier_signal -1
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; OPT-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; OPT-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
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; OPT-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; OPT-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
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; OPT-NEXT: s_barrier_wait -1
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; OPT-NEXT: global_load_b32 v0, v[0:1], off
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; OPT-NEXT: s_wait_loadcnt 0x0
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; OPT-NEXT: global_store_b32 v2, v0, s[0:1]
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; OPT-NEXT: s_endpgm
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;
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; NOOPT-LABEL: test_barrier_independent_valu:
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; NOOPT: ; %bb.0: ; %entry
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; NOOPT-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
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; NOOPT-NEXT: v_and_b32_e32 v2, 0x3ff, v0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; NOOPT-NEXT: v_lshlrev_b32_e32 v3, 2, v2
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; NOOPT-NEXT: s_wait_kmcnt 0x0
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; NOOPT-NEXT: v_xad_u32 v0, v2, -1, s2
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; NOOPT-NEXT: global_store_b32 v3, v2, s[0:1]
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; NOOPT-NEXT: s_barrier_signal -1
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; NOOPT-NEXT: s_barrier_wait -1
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; NOOPT-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; NOOPT-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
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; NOOPT-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; NOOPT-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
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; NOOPT-NEXT: global_load_b32 v0, v[0:1], off
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; NOOPT-NEXT: s_wait_loadcnt 0x0
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; NOOPT-NEXT: global_store_b32 v3, v0, s[0:1]
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; NOOPT-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%addr = getelementptr i32, ptr addrspace(1) %out, i32 %tid
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store i32 %tid, ptr addrspace(1) %addr
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call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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%idx_base = sub i32 %size, 1
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%idx = sub i32 %idx_base, %tid
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%read_addr = getelementptr i32, ptr addrspace(1) %out, i32 %idx
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%val = load i32, ptr addrspace(1) %read_addr
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store i32 %val, ptr addrspace(1) %addr
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ret void
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}
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; No independent work - signal/wait should stay adjacent
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define amdgpu_kernel void @test_barrier_no_independent_work(ptr addrspace(3) %lds) #0 {
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; OPT-LABEL: test_barrier_no_independent_work:
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; OPT: ; %bb.0: ; %entry
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; OPT-NEXT: s_load_b32 s0, s[4:5], 0x24
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; OPT-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; OPT-NEXT: s_wait_kmcnt 0x0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; OPT-NEXT: v_lshl_add_u32 v1, v0, 2, s0
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; OPT-NEXT: ds_store_b32 v1, v0
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; OPT-NEXT: s_barrier_signal -1
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; OPT-NEXT: s_barrier_wait -1
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; OPT-NEXT: ds_load_b32 v0, v1
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; OPT-NEXT: s_wait_dscnt 0x0
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; OPT-NEXT: ds_store_b32 v1, v0 offset:4
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; OPT-NEXT: s_endpgm
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;
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; NOOPT-LABEL: test_barrier_no_independent_work:
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; NOOPT: ; %bb.0: ; %entry
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; NOOPT-NEXT: s_load_b32 s0, s[4:5], 0x24
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; NOOPT-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; NOOPT-NEXT: s_wait_kmcnt 0x0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; NOOPT-NEXT: v_lshl_add_u32 v1, v0, 2, s0
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; NOOPT-NEXT: ds_store_b32 v1, v0
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; NOOPT-NEXT: s_barrier_signal -1
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; NOOPT-NEXT: s_barrier_wait -1
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; NOOPT-NEXT: ds_load_b32 v0, v1
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; NOOPT-NEXT: s_wait_dscnt 0x0
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; NOOPT-NEXT: ds_store_b32 v1, v0 offset:4
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; NOOPT-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%addr = getelementptr i32, ptr addrspace(3) %lds, i32 %tid
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store i32 %tid, ptr addrspace(3) %addr
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call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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%val = load i32, ptr addrspace(3) %addr
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%next = add i32 %tid, 1
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%next_addr = getelementptr i32, ptr addrspace(3) %lds, i32 %next
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store i32 %val, ptr addrspace(3) %next_addr
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ret void
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}
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; Multiple barriers
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define amdgpu_kernel void @test_barrier_multiple(ptr addrspace(1) %out, i32 %size) #0 {
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; OPT-LABEL: test_barrier_multiple:
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; OPT: ; %bb.0: ; %entry
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; OPT-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
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; OPT-NEXT: v_and_b32_e32 v1, 0x3ff, v0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; OPT-NEXT: v_lshlrev_b32_e32 v2, 2, v1
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; OPT-NEXT: s_wait_kmcnt 0x0
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; OPT-NEXT: v_xad_u32 v0, v1, -1, s2
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; OPT-NEXT: global_store_b32 v2, v1, s[0:1]
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; OPT-NEXT: s_barrier_signal -1
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; OPT-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; OPT-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
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; OPT-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; OPT-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
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; OPT-NEXT: s_barrier_wait -1
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; OPT-NEXT: global_load_b32 v3, v[0:1], off
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; OPT-NEXT: s_wait_loadcnt 0x0
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; OPT-NEXT: global_store_b32 v2, v3, s[0:1]
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; OPT-NEXT: s_barrier_signal -1
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; OPT-NEXT: s_barrier_wait -1
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; OPT-NEXT: global_load_b32 v0, v[0:1], off offset:-4
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; OPT-NEXT: s_wait_loadcnt 0x0
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; OPT-NEXT: global_store_b32 v2, v0, s[0:1]
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; OPT-NEXT: s_endpgm
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;
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; NOOPT-LABEL: test_barrier_multiple:
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; NOOPT: ; %bb.0: ; %entry
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; NOOPT-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
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; NOOPT-NEXT: v_and_b32_e32 v2, 0x3ff, v0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; NOOPT-NEXT: v_lshlrev_b32_e32 v3, 2, v2
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; NOOPT-NEXT: s_wait_kmcnt 0x0
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; NOOPT-NEXT: v_xad_u32 v0, v2, -1, s2
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; NOOPT-NEXT: global_store_b32 v3, v2, s[0:1]
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; NOOPT-NEXT: s_barrier_signal -1
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; NOOPT-NEXT: s_barrier_wait -1
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; NOOPT-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; NOOPT-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
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; NOOPT-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; NOOPT-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
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; NOOPT-NEXT: global_load_b32 v2, v[0:1], off
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; NOOPT-NEXT: s_wait_loadcnt 0x0
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; NOOPT-NEXT: global_store_b32 v3, v2, s[0:1]
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; NOOPT-NEXT: s_barrier_signal -1
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; NOOPT-NEXT: s_barrier_wait -1
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; NOOPT-NEXT: global_load_b32 v0, v[0:1], off offset:-4
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; NOOPT-NEXT: s_wait_loadcnt 0x0
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; NOOPT-NEXT: global_store_b32 v3, v0, s[0:1]
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; NOOPT-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%addr = getelementptr i32, ptr addrspace(1) %out, i32 %tid
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store i32 %tid, ptr addrspace(1) %addr
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call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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%idx1_base = sub i32 %size, 1
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%idx1 = sub i32 %idx1_base, %tid
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%read_addr1 = getelementptr i32, ptr addrspace(1) %out, i32 %idx1
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%val1 = load i32, ptr addrspace(1) %read_addr1
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store i32 %val1, ptr addrspace(1) %addr
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call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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%idx2_base = sub i32 %size, 2
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%idx2 = sub i32 %idx2_base, %tid
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%read_addr2 = getelementptr i32, ptr addrspace(1) %out, i32 %idx2
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%val2 = load i32, ptr addrspace(1) %read_addr2
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store i32 %val2, ptr addrspace(1) %addr
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ret void
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}
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declare void @llvm.amdgcn.s.barrier.signal(i32) #1
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declare void @llvm.amdgcn.s.barrier.wait(i16) #1
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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attributes #0 = { nounwind }
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attributes #1 = { convergent nounwind }
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attributes #2 = { nounwind readnone }
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