derek.holloway
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75 lines
3.1 KiB
YAML
75 lines
3.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -amdgpu-s-branch-bits=4 -run-pass branch-relaxation %s -o - | FileCheck %s
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# Test that getInstSizeInBytes correctly estimates S_MOV_B64 with 64-bit
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# literal values on targets with 64-bit literal support (gfx1250).
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#
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# Values outside [0, 2^31-1] require 64-bit literal encoding, making the
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# instruction 12 bytes (4-byte opcode + 8-byte literal) instead of 8 bytes
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# (4-byte opcode + 4-byte literal).
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#
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# With -amdgpu-s-branch-bits=4, forward branches can reach at most +7 dwords.
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# Three S_MOV_B64 with 64-bit literals = 3 * 12 = 36 bytes = 9 dwords,
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# which exceeds the 7-dword limit, so the branch must be relaxed.
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#
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# Without the correct size estimation (8 bytes instead of 12), the total
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# would be 3 * 8 = 24 bytes = 6 dwords, fitting within the limit, and
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# relaxation would not occur. In a rare real-world scenario, this could lead to
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# an assembler error where branch size exceeds simm16.
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# The branch is relaxed: the original S_CBRANCH_SCC0 is inverted to
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# S_CBRANCH_SCC1 (skipping the long branch), and a new block (bb.3) is
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# inserted with S_ADD_PC_I64 for the long branch.
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---
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name: s_mov_b64_64bit_literal_size
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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; CHECK-LABEL: name: s_mov_b64_64bit_literal_size
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $sgpr8
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CMP_EQ_U32 $sgpr8, 0, implicit-def $scc
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; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr4_sgpr5 = S_GETPC_B64 post-instr-symbol <mcsymbol >
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; CHECK-NEXT: $sgpr4 = S_ADD_U32 $sgpr4, target-flags(<unknown target flag>) <mcsymbol >, implicit-def $scc
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; CHECK-NEXT: $sgpr5 = S_ADDC_U32 $sgpr5, target-flags(<unknown target flag>) <mcsymbol >, implicit-def $scc, implicit $scc
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; CHECK-NEXT: S_SETPC_B64 $sgpr4_sgpr5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr10_sgpr11 = S_MOV_B64 4294967295
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; CHECK-NEXT: $sgpr12_sgpr13 = S_MOV_B64 2147483648
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; CHECK-NEXT: $sgpr14_sgpr15 = S_MOV_B64 -17
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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liveins: $sgpr8
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S_CMP_EQ_U32 $sgpr8, 0, implicit-def $scc
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S_CBRANCH_SCC0 %bb.2, implicit $scc
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bb.1:
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; S_MOV_B64 with values requiring 64-bit literal encoding (12 bytes each).
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; These values are outside the [0, 2^31-1] range where 32-bit literal
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; can be used, so they need 64-bit literal encoding on gfx1250.
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; 0xFFFFFFFF (4294967295) is in [2^31, 2^32-1].
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; 0x80000000 (2147483648) is exactly 2^31.
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; -17 (0xFFFFFFFFFFFFFFEF) is a negative non-inline constant.
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$sgpr10_sgpr11 = S_MOV_B64 4294967295
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$sgpr12_sgpr13 = S_MOV_B64 2147483648
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$sgpr14_sgpr15 = S_MOV_B64 -17
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bb.2:
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S_ENDPGM 0
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...
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