derek.holloway
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60 lines
2.1 KiB
YAML
60 lines
2.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=register-coalescer -verify-coalescing -o - %s | FileCheck %s
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# Test that an invalid subreg range is not introduced due to the undef
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# %1.sub0 use. An undef use with a subregister index would end up
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# introducing subranges for the empty and full lanemasks.
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---
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name: merge_with_undef_subreg_use_subrange_lanemask_is_invalid
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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stackPtrOffsetReg: '$sgpr32'
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sgprForEXECCopy: '$sgpr100_sgpr101'
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body: |
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; CHECK-LABEL: name: merge_with_undef_subreg_use_subrange_lanemask_is_invalid
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $sgpr8_sgpr9
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
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; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), addrspace 4)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc
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; CHECK-NEXT: S_BRANCH %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef [[S_LOAD_DWORDX4_IMM:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]].sub1:sgpr_128 = COPY undef [[S_LOAD_DWORDX4_IMM]].sub0
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; CHECK-NEXT: S_ENDPGM 0, implicit [[S_LOAD_DWORDX4_IMM]]
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bb.0:
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liveins: $sgpr8_sgpr9
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%0:sgpr_64 = COPY $sgpr8_sgpr9
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%1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), addrspace 4)
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bb.1:
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%2:sgpr_128 = COPY %1
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S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc
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S_BRANCH %bb.2
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bb.2:
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undef %3.sub0:sgpr_128 = S_MOV_B32 0
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%2:sgpr_128 = COPY killed %3
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bb.3:
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%4:sgpr_128 = COPY killed %2
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%4.sub1:sgpr_128 = COPY undef %1.sub0
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S_ENDPGM 0, implicit %4
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...
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