derek.holloway
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65 lines
2.8 KiB
LLVM
65 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O3 -pre-RA-sched=source < %s | FileCheck -check-prefix=RRLIST %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O3 -pre-RA-sched=fast < %s | FileCheck -check-prefix=FAST %s
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define protected amdgpu_kernel void @sccClobber(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %e, ptr addrspace(1) %f, ptr addrspace(1) %pout.coerce) {
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; RRLIST-LABEL: sccClobber:
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; RRLIST: ; %bb.0: ; %entry
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; RRLIST-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
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; RRLIST-NEXT: v_mov_b32_e32 v2, 0
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; RRLIST-NEXT: s_waitcnt lgkmcnt(0)
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; RRLIST-NEXT: s_load_dword s16, s[12:13], 0x0
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; RRLIST-NEXT: s_load_dwordx2 s[0:1], s[10:11], 0x0
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; RRLIST-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0
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; RRLIST-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x44
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; RRLIST-NEXT: s_load_dword s17, s[14:15], 0x0
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; RRLIST-NEXT: s_waitcnt lgkmcnt(0)
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; RRLIST-NEXT: s_min_i32 s8, s16, 0
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; RRLIST-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
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; RRLIST-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
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; RRLIST-NEXT: s_and_b64 s[4:5], vcc, exec
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; RRLIST-NEXT: s_cselect_b32 s4, s16, s17
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; RRLIST-NEXT: s_cmp_eq_u64 s[2:3], s[0:1]
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; RRLIST-NEXT: s_cselect_b32 s0, s8, s4
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; RRLIST-NEXT: v_mov_b32_e32 v0, s0
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; RRLIST-NEXT: global_store_dword v2, v0, s[6:7]
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; RRLIST-NEXT: s_endpgm
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;
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; FAST-LABEL: sccClobber:
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; FAST: ; %bb.0: ; %entry
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; FAST-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
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; FAST-NEXT: v_mov_b32_e32 v2, 0
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; FAST-NEXT: s_waitcnt lgkmcnt(0)
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; FAST-NEXT: s_load_dword s16, s[12:13], 0x0
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; FAST-NEXT: s_load_dwordx2 s[0:1], s[10:11], 0x0
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; FAST-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0
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; FAST-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x44
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; FAST-NEXT: s_load_dword s17, s[14:15], 0x0
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; FAST-NEXT: s_waitcnt lgkmcnt(0)
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; FAST-NEXT: s_min_i32 s8, s16, 0
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; FAST-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
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; FAST-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
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; FAST-NEXT: s_and_b64 s[4:5], vcc, exec
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; FAST-NEXT: s_cselect_b32 s4, s16, s17
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; FAST-NEXT: s_cmp_eq_u64 s[2:3], s[0:1]
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; FAST-NEXT: s_cselect_b32 s0, s8, s4
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; FAST-NEXT: v_mov_b32_e32 v0, s0
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; FAST-NEXT: global_store_dword v2, v0, s[6:7]
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; FAST-NEXT: s_endpgm
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entry:
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%i = load i64, ptr addrspace(1) %a, align 8
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%i.1 = load i64, ptr addrspace(1) %b, align 8
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%i.2 = load i32, ptr addrspace(1) %e, align 4
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%i.3 = load i32, ptr addrspace(1) %f, align 4
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%cmp7.1 = icmp eq i64 %i, %i.1
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%call.1 = tail call noundef i32 @llvm.smin.i32(i32 noundef 0, i32 noundef %i.2)
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%cmp8.1 = icmp slt i64 %i, %i.1
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%cond.1 = select i1 %cmp8.1, i32 %i.2, i32 %i.3
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%cond14.1 = select i1 %cmp7.1, i32 %call.1, i32 %cond.1
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store i32 %cond14.1, ptr addrspace(1) %pout.coerce, align 4
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ret void
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}
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declare i32 @llvm.smin.i32(i32, i32)
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