derek.holloway
7502bf64a4
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201 lines
7.9 KiB
LLVM
201 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; NOTE: The checks for opt are NOT added by the update script. Those
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; checks are looking for the absence of specific metadata, which
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; cannot be expressed reliably by the generated checks.
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefix=ISA
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; RUN: opt --amdgpu-annotate-uniform -S %s | FileCheck %s -check-prefix=UNIFORM
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; RUN: opt --amdgpu-annotate-uniform --si-annotate-control-flow -S %s | FileCheck %s -check-prefix=CONTROLFLOW
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; This module creates a divergent branch in block Flow2. The branch is
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; marked as divergent by the divergence analysis but the condition is
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; not. This test ensures that the divergence of the branch is tested,
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; not its condition, so that branch is correctly emitted as divergent.
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target triple = "amdgcn-mesa-mesa3d"
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define amdgpu_ps void @main(i32 %0, float %1) {
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; ISA-LABEL: main:
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; ISA: ; %bb.0: ; %start
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; ISA-NEXT: v_readfirstlane_b32 s0, v0
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; ISA-NEXT: s_mov_b32 m0, s0
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; ISA-NEXT: s_mov_b32 s8, 0
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; ISA-NEXT: v_interp_p1_f32_e32 v0, v1, attr0.x
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; ISA-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0
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; ISA-NEXT: s_mov_b64 s[0:1], 0
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; ISA-NEXT: ; implicit-def: $sgpr4_sgpr5
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; ISA-NEXT: ; implicit-def: $sgpr2_sgpr3
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; ISA-NEXT: s_branch .LBB0_3
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; ISA-NEXT: .LBB0_1: ; %Flow1
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; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1
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; ISA-NEXT: s_or_b64 exec, exec, s[4:5]
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; ISA-NEXT: s_mov_b64 s[4:5], s[6:7]
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; ISA-NEXT: s_mov_b64 s[6:7], 0
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; ISA-NEXT: .LBB0_2: ; %Flow
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; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1
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; ISA-NEXT: s_and_b64 s[10:11], exec, s[4:5]
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; ISA-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1]
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; ISA-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
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; ISA-NEXT: s_and_b64 s[6:7], s[6:7], exec
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; ISA-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
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; ISA-NEXT: s_andn2_b64 exec, exec, s[0:1]
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; ISA-NEXT: s_cbranch_execz .LBB0_7
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; ISA-NEXT: .LBB0_3: ; %loop
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; ISA-NEXT: ; =>This Inner Loop Header: Depth=1
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; ISA-NEXT: s_or_b64 s[4:5], s[4:5], exec
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; ISA-NEXT: s_cmp_lt_u32 s8, 32
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; ISA-NEXT: s_mov_b64 s[6:7], -1
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; ISA-NEXT: s_cbranch_scc0 .LBB0_6
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; ISA-NEXT: ; %bb.4: ; %endif1
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; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1
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; ISA-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; ISA-NEXT: s_cbranch_execz .LBB0_1
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; ISA-NEXT: ; %bb.5: ; %endif2
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; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1
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; ISA-NEXT: s_add_i32 s8, s8, 1
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; ISA-NEXT: s_xor_b64 s[6:7], exec, -1
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; ISA-NEXT: s_branch .LBB0_1
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; ISA-NEXT: .LBB0_6: ; in Loop: Header=BB0_3 Depth=1
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; ISA-NEXT: ; implicit-def: $sgpr8
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; ISA-NEXT: s_branch .LBB0_2
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; ISA-NEXT: .LBB0_7: ; %Flow2
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; ISA-NEXT: s_or_b64 exec, exec, s[0:1]
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; ISA-NEXT: v_mov_b32_e32 v1, 0
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; ISA-NEXT: s_and_saveexec_b64 s[0:1], s[2:3]
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; ISA-NEXT: ; %bb.8: ; %if1
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; ISA-NEXT: v_sqrt_f32_e32 v1, v0
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; ISA-NEXT: ; %bb.9: ; %endloop
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; ISA-NEXT: s_or_b64 exec, exec, s[0:1]
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; ISA-NEXT: exp mrt0, v1, v1, v1, v1 done vm
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; ISA-NEXT: s_endpgm
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start:
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%v0 = call float @llvm.amdgcn.interp.p1(float %1, i32 0, i32 0, i32 %0)
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br label %loop
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loop: ; preds = %Flow, %start
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%v1 = phi i32 [ 0, %start ], [ %6, %Flow ]
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%v2 = icmp ugt i32 %v1, 31
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%2 = xor i1 %v2, true
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br i1 %2, label %endif1, label %Flow
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Flow1: ; preds = %endif2, %endif1
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%3 = phi i32 [ %v5, %endif2 ], [ poison, %endif1 ]
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%4 = phi i1 [ false, %endif2 ], [ true, %endif1 ]
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br label %Flow
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; UNIFORM-LABEL: Flow2:
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; UNIFORM-NEXT: br i1 %8, label %if1, label %endloop
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; UNIFORM-NOT: !amdgpu.uniform
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; UNIFORM: if1:
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; CONTROLFLOW-LABEL: Flow2:
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; CONTROLFLOW-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %{{.*}})
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; CONTROLFLOW-NEXT: [[IF:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %{{.*}})
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; CONTROLFLOW-NEXT: [[COND:%.*]] = extractvalue { i1, i64 } [[IF]], 0
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; CONTROLFLOW-NEXT: %{{.*}} = extractvalue { i1, i64 } [[IF]], 1
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; CONTROLFLOW-NEXT: br i1 [[COND]], label %if1, label %endloop
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Flow2: ; preds = %Flow
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br i1 %8, label %if1, label %endloop
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if1: ; preds = %Flow2
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%v3 = call afn float @llvm.sqrt.f32(float %v0)
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br label %endloop
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endif1: ; preds = %loop
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%v4 = fcmp ogt float %v0, 0.000000e+00
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%5 = xor i1 %v4, true
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br i1 %5, label %endif2, label %Flow1
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Flow: ; preds = %Flow1, %loop
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%6 = phi i32 [ %3, %Flow1 ], [ poison, %loop ]
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%7 = phi i1 [ %4, %Flow1 ], [ true, %loop ]
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%8 = phi i1 [ false, %Flow1 ], [ true, %loop ]
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br i1 %7, label %Flow2, label %loop
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endif2: ; preds = %endif1
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%v5 = add i32 %v1, 1
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br label %Flow1
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endloop: ; preds = %if1, %Flow2
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%v6 = phi float [ 0.000000e+00, %Flow2 ], [ %v3, %if1 ]
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %v6, float %v6, float %v6, float %v6, i1 true, i1 true)
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ret void
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}
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define amdgpu_ps void @i1_copy_assert(i1 %v4) {
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; ISA-LABEL: i1_copy_assert:
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; ISA: ; %bb.0: ; %start
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; ISA-NEXT: v_and_b32_e32 v0, 1, v0
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; ISA-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; ISA-NEXT: s_mov_b32 s8, 0
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; ISA-NEXT: s_mov_b64 s[0:1], 0
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; ISA-NEXT: ; implicit-def: $sgpr4_sgpr5
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; ISA-NEXT: ; implicit-def: $sgpr2_sgpr3
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; ISA-NEXT: s_branch .LBB1_3
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; ISA-NEXT: .LBB1_1: ; %endif1
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; ISA-NEXT: ; in Loop: Header=BB1_3 Depth=1
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; ISA-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
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; ISA-NEXT: s_and_b64 s[8:9], vcc, exec
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; ISA-NEXT: s_mov_b64 s[6:7], 0
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; ISA-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
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; ISA-NEXT: .LBB1_2: ; %Flow
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; ISA-NEXT: ; in Loop: Header=BB1_3 Depth=1
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; ISA-NEXT: s_and_b64 s[8:9], exec, s[4:5]
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; ISA-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
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; ISA-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
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; ISA-NEXT: s_and_b64 s[6:7], s[6:7], exec
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; ISA-NEXT: s_mov_b32 s8, 1
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; ISA-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
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; ISA-NEXT: s_andn2_b64 exec, exec, s[0:1]
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; ISA-NEXT: s_cbranch_execz .LBB1_5
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; ISA-NEXT: .LBB1_3: ; %loop
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; ISA-NEXT: ; =>This Inner Loop Header: Depth=1
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; ISA-NEXT: s_or_b64 s[4:5], s[4:5], exec
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; ISA-NEXT: s_cmp_lg_u32 s8, 0
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; ISA-NEXT: s_cbranch_scc1 .LBB1_1
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; ISA-NEXT: ; %bb.4: ; in Loop: Header=BB1_3 Depth=1
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; ISA-NEXT: s_mov_b64 s[6:7], -1
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; ISA-NEXT: s_branch .LBB1_2
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; ISA-NEXT: .LBB1_5: ; %Flow2
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; ISA-NEXT: s_or_b64 exec, exec, s[0:1]
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; ISA-NEXT: v_mov_b32_e32 v0, 0
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; ISA-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[2:3]
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; ISA-NEXT: exp mrt0, off, off, off, off
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; ISA-NEXT: s_endpgm
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start:
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br label %loop
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loop: ; preds = %Flow, %start
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%v1 = phi i32 [ 0, %start ], [ 1, %Flow ]
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%v2 = icmp ugt i32 %v1, 0
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br i1 %v2, label %endif1, label %Flow
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Flow2: ; preds = %Flow
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%spec.select = select i1 %i1, float 1.000000e+00, float 0.000000e+00
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call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float %spec.select, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, i1 false, i1 false)
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ret void
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endif1: ; preds = %loop
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br label %Flow
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Flow: ; preds = %endif1, %loop
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%i = phi i1 [ %v4, %endif1 ], [ true, %loop ]
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%i1 = phi i1 [ false, %endif1 ], [ true, %loop ]
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br i1 %i, label %Flow2, label %loop
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}
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; Function Attrs: nounwind readnone speculatable willreturn
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declare float @llvm.sqrt.f32(float) #0
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; Function Attrs: nounwind readnone speculatable
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declare float @llvm.amdgcn.interp.p1(float, i32 immarg, i32 immarg, i32) #1
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; Function Attrs: inaccessiblememonly nounwind writeonly
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declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #2
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attributes #0 = { nounwind readnone speculatable willreturn }
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attributes #1 = { nounwind readnone speculatable }
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attributes #2 = { inaccessiblememonly nounwind writeonly }
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