derek.holloway
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66 lines
3.0 KiB
YAML
66 lines
3.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck %s
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# Test that si-fix-sgpr-copies preserves the Lo256 register class constraint
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# when eliminating a VGPR-to-SGPR copy used as a WMMA scale operand.
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#
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# The scale_src0 and scale_src1 operands of V_WMMA_SCALE instructions require
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# registers from VCSrc_b32_Lo256 (VS_32_Lo256), which only allows VGPRs 0-255.
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# When si-fix-sgpr-copies eliminates a VGPR-to-SGPR copy by replacing uses of
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# the SGPR with the VGPR source, it must constrain the VGPR to vgpr_32_lo256
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# to preserve this hardware encoding requirement.
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---
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name: wmma_scale_copy_vgpr_to_sgpr
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; CHECK-LABEL: name: wmma_scale_copy_vgpr_to_sgpr
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; CHECK: liveins: $vgpr0, $sgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32_lo256 = COPY $vgpr0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_256_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF3:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
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; CHECK-NEXT: early-clobber %6:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr [[DEF]], [[DEF1]], 0, [[DEF2]], [[COPY]], [[DEF3]], 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0
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%0:vgpr_32 = COPY $vgpr0
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%1:sreg_32 = COPY %0
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%2:vreg_512_align2 = IMPLICIT_DEF
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%3:vreg_512_align2 = IMPLICIT_DEF
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%4:vreg_256_align2 = IMPLICIT_DEF
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%5:vgpr_32_lo256 = IMPLICIT_DEF
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%6:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr %2, %3, 0, %4, %1, %5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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# Also test scale_src1 (operand 6) constraint is preserved.
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---
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name: wmma_scale_copy_vgpr_to_sgpr_src1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; CHECK-LABEL: name: wmma_scale_copy_vgpr_to_sgpr_src1
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; CHECK: liveins: $vgpr0, $sgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32_lo256 = COPY $vgpr0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_256_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF3:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
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; CHECK-NEXT: early-clobber %6:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr [[DEF]], [[DEF1]], 0, [[DEF2]], [[DEF3]], [[COPY]], 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0
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%0:vgpr_32 = COPY $vgpr0
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%1:sreg_32 = COPY %0
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%2:vreg_512_align2 = IMPLICIT_DEF
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%3:vreg_512_align2 = IMPLICIT_DEF
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%4:vreg_256_align2 = IMPLICIT_DEF
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%5:vgpr_32_lo256 = IMPLICIT_DEF
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%6:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr %2, %3, 0, %4, %5, %1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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