derek.holloway
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158 lines
5.9 KiB
LLVM
158 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 %s
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define amdgpu_kernel void @fneg_fabsf_fadd_f32(ptr addrspace(1) %out, float %x, float %y) {
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; R600-LABEL: fneg_fabsf_fadd_f32:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
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; R600-NEXT: ADD * T1.X, KC0[2].W, -|KC0[2].Z|,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%fabs = call float @llvm.fabs.f32(float %x)
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%fsub = fsub float -0.000000e+00, %fabs
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%fadd = fadd float %y, %fsub
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store float %fadd, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @fneg_fabsf_fmul_f32(ptr addrspace(1) %out, float %x, float %y) {
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; R600-LABEL: fneg_fabsf_fmul_f32:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
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; R600-NEXT: MUL_IEEE * T1.X, KC0[2].W, -|KC0[2].Z|,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%fabs = call float @llvm.fabs.f32(float %x)
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%fsub = fsub float -0.000000e+00, %fabs
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%fmul = fmul float %y, %fsub
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store float %fmul, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @fneg_fabsf_free_f32(ptr addrspace(1) %out, i32 %in) {
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; R600-LABEL: fneg_fabsf_free_f32:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: MOV * T0.W, KC0[2].Z,
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; R600-NEXT: MOV * T0.W, |PV.W|,
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; R600-NEXT: MOV T0.X, -PV.W,
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; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%bc = bitcast i32 %in to float
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%fabs = call float @llvm.fabs.f32(float %bc)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fneg_fabsf_f32(ptr addrspace(1) %out, float %in) {
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; R600-LABEL: fneg_fabsf_f32:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: MOV * T0.W, KC0[2].Z,
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; R600-NEXT: MOV * T0.W, |PV.W|,
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; R600-NEXT: MOV T0.X, -PV.W,
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; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%fabs = call float @llvm.fabs.f32(float %in)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @v_fneg_fabsf_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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; R600-LABEL: v_fneg_fabsf_f32:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
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; R600-NEXT: TEX 0 @6
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; R600-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: Fetch clause starting at 6:
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; R600-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
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; R600-NEXT: ALU clause starting at 8:
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; R600-NEXT: MOV * T0.X, KC0[2].Z,
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; R600-NEXT: ALU clause starting at 9:
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; R600-NEXT: MOV * T0.W, |T0.X|,
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; R600-NEXT: MOV T0.X, -PV.W,
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; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%val = load float, ptr addrspace(1) %in, align 4
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%fabs = call float @llvm.fabs.f32(float %val)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @fneg_fabsf_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
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; R600-LABEL: fneg_fabsf_v2f32:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: MOV T0.W, KC0[3].X,
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; R600-NEXT: MOV * T1.W, KC0[2].W,
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; R600-NEXT: MOV * T0.W, |PV.W|,
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; R600-NEXT: MOV T0.Y, -PV.W,
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; R600-NEXT: MOV * T0.W, |T1.W|,
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; R600-NEXT: MOV T0.X, -PV.W,
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; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
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%fsub = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %fabs
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store <2 x float> %fsub, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fneg_fabsf_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
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; R600-LABEL: fneg_fabsf_v4f32:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: MOV * T0.W, KC0[4].X,
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; R600-NEXT: MOV T0.W, |PV.W|,
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; R600-NEXT: MOV * T1.W, KC0[3].W,
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; R600-NEXT: MOV T0.Z, KC0[3].Z,
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; R600-NEXT: MOV T1.W, |PS|,
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; R600-NEXT: MOV * T2.W, -PV.W,
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; R600-NEXT: MOV T2.Z, -PV.W,
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; R600-NEXT: MOV T0.W, KC0[3].Y,
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; R600-NEXT: MOV * T1.W, |PV.Z|,
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; R600-NEXT: MOV T2.Y, -PS,
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; R600-NEXT: MOV * T0.W, |PV.W|,
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; R600-NEXT: MOV T2.X, -PV.W,
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; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
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%fsub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %fabs
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store <4 x float> %fsub, ptr addrspace(1) %out
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ret void
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}
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declare float @llvm.fabs.f32(float) readnone
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declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
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