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129 lines
4.5 KiB
YAML
129 lines
4.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
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# The constant is 0xffffffff80000000. It is 64-bit negative constant, but it passes the test
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# isInt<32>(). Nonetheless it is not a legal literal for a binary or unsigned operand and
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# cannot be used right in the shift as HW will zero extend it.
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---
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name: imm64_shift_int32_const_0xffffffff80000000
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body: |
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bb.0:
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; GCN-LABEL: name: imm64_shift_int32_const_0xffffffff80000000
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; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -2147483648
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; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
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; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
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%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744071562067968
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%1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
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S_ENDPGM 0, implicit %1
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...
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---
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name: imm64_shift_int32_const_0xffffffff
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body: |
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bb.0:
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; GCN-LABEL: name: imm64_shift_int32_const_0xffffffff
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; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
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; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
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; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
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%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
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%1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
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S_ENDPGM 0, implicit %1
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...
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---
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name: imm64_shift_int32_const_0x80000000
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body: |
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bb.0:
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; GCN-LABEL: name: imm64_shift_int32_const_0x80000000
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; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483648
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; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
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; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
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%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483648
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%1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
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S_ENDPGM 0, implicit %1
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...
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---
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name: imm64_shift_int32_const_0x7fffffff
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body: |
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bb.0:
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; GCN-LABEL: name: imm64_shift_int32_const_0x7fffffff
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; GCN: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 2147483647, 1, implicit-def $scc
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; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
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%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483647
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%1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
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S_ENDPGM 0, implicit %1
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...
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---
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name: imm64_shift_int32_const_0x1ffffffff
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body: |
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bb.0:
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; GCN-LABEL: name: imm64_shift_int32_const_0x1ffffffff
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; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 8589934591
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; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
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; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
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%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 8589934591
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%1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
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S_ENDPGM 0, implicit %1
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...
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---
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name: imm64_shift_int32_const_0xffffffffffffffff
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body: |
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bb.0:
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; GCN-LABEL: name: imm64_shift_int32_const_0xffffffffffffffff
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; GCN: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 -1, 1, implicit-def $scc
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; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
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%0:sreg_64 = S_MOV_B64_IMM_PSEUDO -1
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%1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
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S_ENDPGM 0, implicit %1
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...
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---
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name: imm64_ashr_int32_const_0xffffffff
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body: |
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bb.0:
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; GCN-LABEL: name: imm64_ashr_int32_const_0xffffffff
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; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
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; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[S_MOV_B]], 1, implicit-def $scc
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; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
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%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
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%1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc
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S_ENDPGM 0, implicit %1
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...
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---
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name: imm64_ashr_int32_const_0x7fffffff
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body: |
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bb.0:
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; GCN-LABEL: name: imm64_ashr_int32_const_0x7fffffff
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; GCN: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 2147483647, 1, implicit-def $scc
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; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
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%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483647
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%1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc
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S_ENDPGM 0, implicit %1
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...
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---
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name: imm64_ashr_int32_const_0xffffffffffffffff
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body: |
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bb.0:
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; GCN-LABEL: name: imm64_ashr_int32_const_0xffffffffffffffff
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; GCN: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 -1, 1, implicit-def $scc
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; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
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%0:sreg_64 = S_MOV_B64_IMM_PSEUDO -1
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%1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc
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S_ENDPGM 0, implicit %1
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...
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