derek.holloway
7502bf64a4
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207 lines
9.2 KiB
LLVM
207 lines
9.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn--amdpal -mcpu=gfx1250 < %s | FileCheck %s --check-prefix=GISEL
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; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx1250 < %s | FileCheck %s --check-prefix=DAGISEL
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn--amdpal -mcpu=gfx1250 < %s | FileCheck %s --check-prefix=NRBS
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declare i1 @llvm.amdgcn.s.alloc.vgpr(i32)
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define amdgpu_cs void @test_alloc_vreg_const(ptr addrspace(1) %out) #0 {
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; GISEL-LABEL: test_alloc_vreg_const:
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; GISEL: ; %bb.0: ; %entry
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; GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GISEL-NEXT: v_nop
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; GISEL-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
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; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
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; GISEL-NEXT: s_cmp_lg_u32 0, s33
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; GISEL-NEXT: s_cmovk_i32 s33, 0x1c0
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; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GISEL-NEXT: s_alloc_vgpr 45
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; GISEL-NEXT: s_cselect_b32 s0, 1, 0
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; GISEL-NEXT: s_and_b32 s0, s0, 1
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; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
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; GISEL-NEXT: s_cmp_lg_u32 s0, 0
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; GISEL-NEXT: s_cselect_b32 s0, 1, 0
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; GISEL-NEXT: v_mov_b32_e32 v2, s0
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; GISEL-NEXT: global_store_b32 v[0:1], v2, off
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; GISEL-NEXT: s_alloc_vgpr 0
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; GISEL-NEXT: s_endpgm
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;
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; DAGISEL-LABEL: test_alloc_vreg_const:
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; DAGISEL: ; %bb.0: ; %entry
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; DAGISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; DAGISEL-NEXT: v_nop
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; DAGISEL-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
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; DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
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; DAGISEL-NEXT: s_cmp_lg_u32 0, s33
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; DAGISEL-NEXT: s_cmovk_i32 s33, 0x1c0
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; DAGISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; DAGISEL-NEXT: s_alloc_vgpr 45
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; DAGISEL-NEXT: s_cselect_b32 s0, -1, 0
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; DAGISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
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; DAGISEL-NEXT: global_store_b32 v[0:1], v2, off
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; DAGISEL-NEXT: s_alloc_vgpr 0
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; DAGISEL-NEXT: s_endpgm
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;
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; NRBS-LABEL: test_alloc_vreg_const:
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; NRBS: ; %bb.0: ; %entry
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; NRBS-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; NRBS-NEXT: v_nop
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; NRBS-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
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; NRBS-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
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; NRBS-NEXT: s_cmp_lg_u32 0, s33
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; NRBS-NEXT: s_cmovk_i32 s33, 0x1c0
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; NRBS-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; NRBS-NEXT: s_alloc_vgpr 45
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; NRBS-NEXT: s_cselect_b32 s0, 1, 0
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; NRBS-NEXT: s_and_b32 s0, s0, 1
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; NRBS-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
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; NRBS-NEXT: s_cmp_lg_u32 s0, 0
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; NRBS-NEXT: s_cselect_b32 s0, 1, 0
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; NRBS-NEXT: v_mov_b32_e32 v2, s0
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; NRBS-NEXT: global_store_b32 v[0:1], v2, off
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; NRBS-NEXT: s_alloc_vgpr 0
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; NRBS-NEXT: s_endpgm
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entry:
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%scc = call i1 @llvm.amdgcn.s.alloc.vgpr(i32 45)
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%sel = select i1 %scc, i32 1, i32 0
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_cs void @test_alloc_vreg_var(i32 inreg %n, ptr addrspace(1) %out) #0 {
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; GISEL-LABEL: test_alloc_vreg_var:
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; GISEL: ; %bb.0: ; %entry
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; GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GISEL-NEXT: v_nop
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; GISEL-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
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; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
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; GISEL-NEXT: s_cmp_lg_u32 0, s33
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; GISEL-NEXT: s_cmovk_i32 s33, 0x1c0
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; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GISEL-NEXT: s_alloc_vgpr s0
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; GISEL-NEXT: s_cselect_b32 s0, 1, 0
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; GISEL-NEXT: s_and_b32 s0, s0, 1
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; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
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; GISEL-NEXT: s_cmp_lg_u32 s0, 0
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; GISEL-NEXT: s_cselect_b32 s0, 1, 0
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; GISEL-NEXT: v_mov_b32_e32 v2, s0
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; GISEL-NEXT: global_store_b32 v[0:1], v2, off
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; GISEL-NEXT: s_alloc_vgpr 0
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; GISEL-NEXT: s_endpgm
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;
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; DAGISEL-LABEL: test_alloc_vreg_var:
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; DAGISEL: ; %bb.0: ; %entry
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; DAGISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; DAGISEL-NEXT: v_nop
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; DAGISEL-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
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; DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
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; DAGISEL-NEXT: s_cmp_lg_u32 0, s33
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; DAGISEL-NEXT: s_cmovk_i32 s33, 0x1c0
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; DAGISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; DAGISEL-NEXT: s_alloc_vgpr s0
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; DAGISEL-NEXT: s_cselect_b32 s0, -1, 0
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; DAGISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
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; DAGISEL-NEXT: global_store_b32 v[0:1], v2, off
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; DAGISEL-NEXT: s_alloc_vgpr 0
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; DAGISEL-NEXT: s_endpgm
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;
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; NRBS-LABEL: test_alloc_vreg_var:
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; NRBS: ; %bb.0: ; %entry
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; NRBS-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; NRBS-NEXT: v_nop
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; NRBS-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
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; NRBS-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
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; NRBS-NEXT: s_cmp_lg_u32 0, s33
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; NRBS-NEXT: s_cmovk_i32 s33, 0x1c0
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; NRBS-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; NRBS-NEXT: s_alloc_vgpr s0
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; NRBS-NEXT: s_cselect_b32 s0, 1, 0
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; NRBS-NEXT: s_and_b32 s0, s0, 1
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; NRBS-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
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; NRBS-NEXT: s_cmp_lg_u32 s0, 0
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; NRBS-NEXT: s_cselect_b32 s0, 1, 0
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; NRBS-NEXT: v_mov_b32_e32 v2, s0
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; NRBS-NEXT: global_store_b32 v[0:1], v2, off
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; NRBS-NEXT: s_alloc_vgpr 0
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; NRBS-NEXT: s_endpgm
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entry:
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%scc = call i1 @llvm.amdgcn.s.alloc.vgpr(i32 %n)
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%sel = select i1 %scc, i32 1, i32 0
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_cs void @test_alloc_vreg_vgpr(i32 %n, ptr addrspace(1) %out) #0 {
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; GISEL-LABEL: test_alloc_vreg_vgpr:
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; GISEL: ; %bb.0: ; %entry
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; GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GISEL-NEXT: v_nop
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; GISEL-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
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; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GISEL-NEXT: s_cmp_lg_u32 0, s33
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; GISEL-NEXT: s_cmovk_i32 s33, 0x1c0
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; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GISEL-NEXT: v_readfirstlane_b32 s0, v0
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; GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
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; GISEL-NEXT: s_alloc_vgpr s0
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; GISEL-NEXT: s_cselect_b32 s0, 1, 0
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; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GISEL-NEXT: s_and_b32 s0, s0, 1
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; GISEL-NEXT: s_cmp_lg_u32 s0, 0
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; GISEL-NEXT: s_cselect_b32 s0, 1, 0
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; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GISEL-NEXT: v_mov_b32_e32 v0, s0
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; GISEL-NEXT: global_store_b32 v[4:5], v0, off
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; GISEL-NEXT: s_alloc_vgpr 0
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; GISEL-NEXT: s_endpgm
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;
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; DAGISEL-LABEL: test_alloc_vreg_vgpr:
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; DAGISEL: ; %bb.0: ; %entry
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; DAGISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; DAGISEL-NEXT: v_nop
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; DAGISEL-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
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; DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; DAGISEL-NEXT: s_cmp_lg_u32 0, s33
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; DAGISEL-NEXT: s_cmovk_i32 s33, 0x1c0
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; DAGISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; DAGISEL-NEXT: v_readfirstlane_b32 s0, v0
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; DAGISEL-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
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; DAGISEL-NEXT: s_alloc_vgpr s0
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; DAGISEL-NEXT: s_cselect_b32 s0, -1, 0
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; DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; DAGISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
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; DAGISEL-NEXT: global_store_b32 v[2:3], v0, off
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; DAGISEL-NEXT: s_alloc_vgpr 0
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; DAGISEL-NEXT: s_endpgm
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;
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; NRBS-LABEL: test_alloc_vreg_vgpr:
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; NRBS: ; %bb.0: ; %entry
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; NRBS-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; NRBS-NEXT: v_nop
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; NRBS-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
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; NRBS-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; NRBS-NEXT: s_cmp_lg_u32 0, s33
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; NRBS-NEXT: s_cmovk_i32 s33, 0x1c0
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; NRBS-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; NRBS-NEXT: v_readfirstlane_b32 s0, v0
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; NRBS-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
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; NRBS-NEXT: s_alloc_vgpr s0
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; NRBS-NEXT: s_cselect_b32 s0, 1, 0
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; NRBS-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; NRBS-NEXT: s_and_b32 s0, s0, 1
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; NRBS-NEXT: s_cmp_lg_u32 s0, 0
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; NRBS-NEXT: s_cselect_b32 s0, 1, 0
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; NRBS-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; NRBS-NEXT: v_mov_b32_e32 v0, s0
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; NRBS-NEXT: global_store_b32 v[4:5], v0, off
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; NRBS-NEXT: s_alloc_vgpr 0
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; NRBS-NEXT: s_endpgm
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entry:
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%scc = call i1 @llvm.amdgcn.s.alloc.vgpr(i32 %n)
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%sel = select i1 %scc, i32 1, i32 0
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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attributes #0 = { "amdgpu-dynamic-vgpr-block-size" = "16" }
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