derek.holloway
7502bf64a4
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312 lines
15 KiB
LLVM
312 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
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declare i32 @llvm.amdgcn.cvt.pk.fp8.f32.e5m3(float, float, i32, i1)
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declare i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float, i32, i32, i32)
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declare float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32, i32)
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define i32 @test_cvt_pk_fp8_f32_word0(float %x, float %y, i32 %old) {
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; GFX1250-TRUE16-LABEL: test_cvt_pk_fp8_f32_word0:
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; GFX1250-TRUE16: ; %bb.0:
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; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.l, v0, v1 clamp
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; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, v2
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; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
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;
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; GFX1250-FAKE16-LABEL: test_cvt_pk_fp8_f32_word0:
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; GFX1250-FAKE16: ; %bb.0:
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; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 clamp
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; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, v2
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; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
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;
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; GFX1250-GISEL-LABEL: test_cvt_pk_fp8_f32_word0:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX1250-GISEL-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 clamp
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, v2
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; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
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%ret = tail call i32 @llvm.amdgcn.cvt.pk.fp8.f32.e5m3(float %x, float %y, i32 %old, i1 false)
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ret i32 %ret
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}
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define i32 @test_cvt_pk_fp8_f32_word1(float %x, float %y, i32 %old) {
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; GFX1250-TRUE16-LABEL: test_cvt_pk_fp8_f32_word1:
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; GFX1250-TRUE16: ; %bb.0:
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; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.h, v0, v1 clamp
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; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, v2
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; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
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;
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; GFX1250-FAKE16-LABEL: test_cvt_pk_fp8_f32_word1:
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; GFX1250-FAKE16: ; %bb.0:
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; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 op_sel:[0,0,1] clamp
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; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, v2
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; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
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;
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; GFX1250-GISEL-LABEL: test_cvt_pk_fp8_f32_word1:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX1250-GISEL-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 op_sel:[0,0,1] clamp
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, v2
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; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
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%ret = tail call i32 @llvm.amdgcn.cvt.pk.fp8.f32.e5m3(float %x, float %y, i32 %old, i1 true)
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ret i32 %ret
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}
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define amdgpu_cs void @test_cvt_pk_fp8_f32_word1_dpp(i32 %a, float %y, i32 %old, ptr addrspace(1) %out) {
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; GFX1250-TRUE16-LABEL: test_cvt_pk_fp8_f32_word1_dpp:
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; GFX1250-TRUE16: ; %bb.0:
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; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-TRUE16-NEXT: v_nop
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; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-TRUE16-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
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; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
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; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.h, v0, v1 clamp
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; GFX1250-TRUE16-NEXT: global_store_b32 v[4:5], v2, off
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; GFX1250-TRUE16-NEXT: s_endpgm
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;
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; GFX1250-FAKE16-LABEL: test_cvt_pk_fp8_f32_word1_dpp:
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; GFX1250-FAKE16: ; %bb.0:
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; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-FAKE16-NEXT: v_nop
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; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-FAKE16-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
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; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
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; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 op_sel:[0,0,1] clamp
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; GFX1250-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
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; GFX1250-FAKE16-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: test_cvt_pk_fp8_f32_word1_dpp:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
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; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX1250-GISEL-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 op_sel:[0,0,1] clamp
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; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v2, off
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; GFX1250-GISEL-NEXT: s_endpgm
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%tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)
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%tmp1 = bitcast i32 %tmp0 to float
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%ret = tail call i32 @llvm.amdgcn.cvt.pk.fp8.f32.e5m3(float %tmp1, float %y, i32 %old, i1 true)
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store i32 %ret, ptr addrspace(1) %out
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ret void
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}
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define i32 @test_cvt_sr_fp8_f32_byte0(float %x, i32 %r, i32 %old) {
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; GFX1250-LABEL: test_cvt_sr_fp8_f32_byte0:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 clamp
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-NEXT: v_mov_b32_e32 v0, v2
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float %x, i32 %r, i32 %old, i32 0)
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ret i32 %ret
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}
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define i32 @test_cvt_sr_fp8_f32_byte1(float %x, i32 %r, i32 %old) {
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; GFX1250-LABEL: test_cvt_sr_fp8_f32_byte1:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 byte_sel:1 clamp
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-NEXT: v_mov_b32_e32 v0, v2
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float %x, i32 %r, i32 %old, i32 1)
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ret i32 %ret
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}
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define i32 @test_cvt_sr_fp8_f32_byte2(float %x, i32 %r, i32 %old) {
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; GFX1250-LABEL: test_cvt_sr_fp8_f32_byte2:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 byte_sel:2 clamp
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-NEXT: v_mov_b32_e32 v0, v2
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float %x, i32 %r, i32 %old, i32 2)
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ret i32 %ret
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}
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define i32 @test_cvt_sr_fp8_f32_byte3(float %x, i32 %r, i32 %old) {
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; GFX1250-LABEL: test_cvt_sr_fp8_f32_byte3:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 byte_sel:3 clamp
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-NEXT: v_mov_b32_e32 v0, v2
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float %x, i32 %r, i32 %old, i32 3)
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ret i32 %ret
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}
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define amdgpu_cs void @test_cvt_sr_fp8_f32_byte1_dpp(i32 %a, i32 %r, i32 %old, ptr addrspace(1) %out) {
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; GFX1250-TRUE16-LABEL: test_cvt_sr_fp8_f32_byte1_dpp:
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; GFX1250-TRUE16: ; %bb.0:
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; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-TRUE16-NEXT: v_nop
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; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
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; GFX1250-TRUE16-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 clamp quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
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; GFX1250-TRUE16-NEXT: global_store_b32 v[4:5], v2, off
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; GFX1250-TRUE16-NEXT: s_endpgm
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;
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; GFX1250-FAKE16-LABEL: test_cvt_sr_fp8_f32_byte1_dpp:
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; GFX1250-FAKE16: ; %bb.0:
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; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-FAKE16-NEXT: v_nop
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; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
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; GFX1250-FAKE16-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 clamp quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
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; GFX1250-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
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; GFX1250-FAKE16-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: test_cvt_sr_fp8_f32_byte1_dpp:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
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; GFX1250-GISEL-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 clamp quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
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; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v2, off
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; GFX1250-GISEL-NEXT: s_endpgm
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%tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)
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%tmp1 = bitcast i32 %tmp0 to float
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%ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float %tmp1, i32 %r, i32 %old, i32 1)
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store i32 %ret, ptr addrspace(1) %out
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ret void
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}
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define float @test_cvt_f32_fp8_e5m3_byte0(i32 %a) {
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; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte0:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 clamp
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 0)
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ret float %ret
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}
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define float @test_cvt_f32_fp8_e5m3_byte1(i32 %a) {
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; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte1:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1 clamp
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 1)
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ret float %ret
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}
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define float @test_cvt_f32_fp8_e5m3_byte2(i32 %a) {
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; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte2:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GFX1250-NEXT: s_wait_kmcnt 0x0
|
|
; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:2 clamp
|
|
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
|
|
%ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 2)
|
|
ret float %ret
|
|
}
|
|
|
|
define float @test_cvt_f32_fp8_e5m3_byte3(i32 %a) {
|
|
; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte3:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GFX1250-NEXT: s_wait_kmcnt 0x0
|
|
; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:3 clamp
|
|
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
|
|
%ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 3)
|
|
ret float %ret
|
|
}
|
|
|
|
define amdgpu_ps i32 @test_cvt_pk_fp8_f32_e5m3_word0_sss(float inreg %x, float inreg %y, i32 inreg %old) {
|
|
; GFX1250-TRUE16-LABEL: test_cvt_pk_fp8_f32_e5m3_word0_sss:
|
|
; GFX1250-TRUE16: ; %bb.0:
|
|
; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-TRUE16-NEXT: v_nop
|
|
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
|
|
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
|
|
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, s0, s1 clamp
|
|
; GFX1250-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX1250-FAKE16-LABEL: test_cvt_pk_fp8_f32_e5m3_word0_sss:
|
|
; GFX1250-FAKE16: ; %bb.0:
|
|
; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-FAKE16-NEXT: v_nop
|
|
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, s2
|
|
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, s0, s1 clamp
|
|
; GFX1250-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX1250-GISEL-LABEL: test_cvt_pk_fp8_f32_e5m3_word0_sss:
|
|
; GFX1250-GISEL: ; %bb.0:
|
|
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-GISEL-NEXT: v_nop
|
|
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s2
|
|
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX1250-GISEL-NEXT: v_cvt_pk_fp8_f32 v0, s0, s1 clamp
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX1250-GISEL-NEXT: ; return to shader part epilog
|
|
%ret = tail call i32 @llvm.amdgcn.cvt.pk.fp8.f32.e5m3(float %x, float %y, i32 %old, i1 false)
|
|
ret i32 %ret
|
|
}
|
|
|
|
define amdgpu_ps i32 @test_cvt_sr_fp8_f32_e5m3_byte0_sss(float inreg %x, i32 inreg %r, i32 inreg %old) {
|
|
; GFX1250-LABEL: test_cvt_sr_fp8_f32_e5m3_byte0_sss:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_mov_b32_e32 v0, s2
|
|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX1250-NEXT: v_cvt_sr_fp8_f32 v0, s0, s1 clamp
|
|
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX1250-NEXT: ; return to shader part epilog
|
|
%ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float %x, i32 %r, i32 %old, i32 0)
|
|
ret i32 %ret
|
|
}
|
|
|
|
define amdgpu_ps float @test_cvt_f32_fp8_e5m3_byte0_s(i32 inreg %a) {
|
|
; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte0_s:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, s0 clamp
|
|
; GFX1250-NEXT: ; return to shader part epilog
|
|
%ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 0)
|
|
ret float %ret
|
|
}
|