derek.holloway
7502bf64a4
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432 lines
18 KiB
LLVM
432 lines
18 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck %s -check-prefixes=SI-SDAG
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck %s -check-prefixes=SI-GISEL
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck %s -check-prefixes=SI-SDAG
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck %s -check-prefixes=SI-GISEL
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck %s -check-prefixes=VI,VI-SDAG
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck %s -check-prefixes=VI,VI-GISEL
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefixes=GFX9,GFX9-SDAG
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefixes=GFX9,GFX9-GISEL
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define amdgpu_kernel void @s_cvt_pk_i16_i32(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {
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; SI-SDAG-LABEL: s_cvt_pk_i16_i32:
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; SI-SDAG: ; %bb.0:
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; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
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; SI-SDAG-NEXT: s_mov_b32 s6, -1
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; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; SI-SDAG-NEXT: v_mov_b32_e32 v0, s3
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; SI-SDAG-NEXT: s_mov_b32 s4, s0
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; SI-SDAG-NEXT: s_mov_b32 s5, s1
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; SI-SDAG-NEXT: v_cvt_pk_i16_i32_e32 v0, s2, v0
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; SI-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; SI-SDAG-NEXT: s_endpgm
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;
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; SI-GISEL-LABEL: s_cvt_pk_i16_i32:
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; SI-GISEL: ; %bb.0:
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; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
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; SI-GISEL-NEXT: v_cvt_pk_i16_i32_e32 v0, s2, v0
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; SI-GISEL-NEXT: s_mov_b32 s2, -1
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; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
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; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-GISEL-NEXT: s_endpgm
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;
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; VI-LABEL: s_cvt_pk_i16_i32:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v0, s3
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; VI-NEXT: v_cvt_pk_i16_i32 v2, s2, v0
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; VI-NEXT: v_mov_b32_e32 v0, s0
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; VI-NEXT: v_mov_b32_e32 v1, s1
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_endpgm
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;
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; GFX9-SDAG-LABEL: s_cvt_pk_i16_i32:
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; GFX9-SDAG: ; %bb.0:
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; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
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; GFX9-SDAG-NEXT: v_cvt_pk_i16_i32 v1, s2, v1
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; GFX9-SDAG-NEXT: global_store_dword v0, v1, s[0:1]
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; GFX9-SDAG-NEXT: s_endpgm
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;
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; GFX9-GISEL-LABEL: s_cvt_pk_i16_i32:
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; GFX9-GISEL: ; %bb.0:
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; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
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; GFX9-GISEL-NEXT: v_cvt_pk_i16_i32 v0, s2, v0
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; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX9-GISEL-NEXT: s_endpgm
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%result = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 %y)
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%r = bitcast <2 x i16> %result to i32
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store i32 %r, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_cvt_pk_i16_samereg_i32(ptr addrspace(1) %out, i32 %x) #0 {
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; SI-SDAG-LABEL: s_cvt_pk_i16_samereg_i32:
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; SI-SDAG: ; %bb.0:
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; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
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; SI-SDAG-NEXT: s_mov_b32 s2, -1
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; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; SI-SDAG-NEXT: v_cvt_pk_i16_i32_e64 v0, s6, s6
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; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-SDAG-NEXT: s_endpgm
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;
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; SI-GISEL-LABEL: s_cvt_pk_i16_samereg_i32:
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; SI-GISEL: ; %bb.0:
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; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
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; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-GISEL-NEXT: s_mov_b32 s2, -1
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; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; SI-GISEL-NEXT: v_cvt_pk_i16_i32_e64 v0, s3, s3
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; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
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; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-GISEL-NEXT: s_endpgm
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;
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; VI-LABEL: s_cvt_pk_i16_samereg_i32:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
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; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_cvt_pk_i16_i32 v2, s2, s2
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; VI-NEXT: v_mov_b32_e32 v0, s0
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; VI-NEXT: v_mov_b32_e32 v1, s1
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_endpgm
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;
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; GFX9-SDAG-LABEL: s_cvt_pk_i16_samereg_i32:
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; GFX9-SDAG: ; %bb.0:
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; GFX9-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-SDAG-NEXT: v_cvt_pk_i16_i32 v1, s2, s2
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; GFX9-SDAG-NEXT: global_store_dword v0, v1, s[0:1]
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; GFX9-SDAG-NEXT: s_endpgm
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;
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; GFX9-GISEL-LABEL: s_cvt_pk_i16_samereg_i32:
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; GFX9-GISEL: ; %bb.0:
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; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-GISEL-NEXT: v_cvt_pk_i16_i32 v0, s2, s2
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; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX9-GISEL-NEXT: s_endpgm
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%result = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 %x)
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%r = bitcast <2 x i16> %result to i32
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store i32 %r, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @v_cvt_pk_i16_i32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
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; SI-SDAG-LABEL: v_cvt_pk_i16_i32:
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; SI-SDAG: ; %bb.0:
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; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
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; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
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; SI-SDAG-NEXT: s_mov_b32 s6, 0
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; SI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; SI-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]
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; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0
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; SI-SDAG-NEXT: s_mov_b64 s[10:11], s[6:7]
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; SI-SDAG-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc
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; SI-SDAG-NEXT: s_waitcnt vmcnt(0)
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; SI-SDAG-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 glc
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; SI-SDAG-NEXT: s_waitcnt vmcnt(0)
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; SI-SDAG-NEXT: s_mov_b64 s[2:3], s[6:7]
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; SI-SDAG-NEXT: v_cvt_pk_i16_i32_e32 v2, v2, v3
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; SI-SDAG-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; SI-SDAG-NEXT: s_endpgm
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;
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; SI-GISEL-LABEL: v_cvt_pk_i16_i32:
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; SI-GISEL: ; %bb.0:
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; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
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; SI-GISEL-NEXT: s_mov_b32 s10, 0
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; SI-GISEL-NEXT: s_mov_b32 s11, 0xf000
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; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0
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; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; SI-GISEL-NEXT: s_mov_b64 s[8:9], s[2:3]
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; SI-GISEL-NEXT: s_mov_b64 s[6:7], s[10:11]
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; SI-GISEL-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
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; SI-GISEL-NEXT: s_waitcnt vmcnt(0)
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; SI-GISEL-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc
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; SI-GISEL-NEXT: s_waitcnt vmcnt(0)
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; SI-GISEL-NEXT: s_mov_b64 s[2:3], s[10:11]
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; SI-GISEL-NEXT: v_cvt_pk_i16_i32_e32 v2, v2, v3
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; SI-GISEL-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; SI-GISEL-NEXT: s_endpgm
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;
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; VI-SDAG-LABEL: v_cvt_pk_i16_i32:
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; VI-SDAG: ; %bb.0:
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; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
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; VI-SDAG-NEXT: v_lshlrev_b32_e32 v4, 2, v0
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; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; VI-SDAG-NEXT: v_mov_b32_e32 v1, s3
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; VI-SDAG-NEXT: v_add_u32_e32 v0, vcc, s2, v4
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; VI-SDAG-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-SDAG-NEXT: v_mov_b32_e32 v3, s5
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; VI-SDAG-NEXT: v_add_u32_e32 v2, vcc, s4, v4
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; VI-SDAG-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; VI-SDAG-NEXT: flat_load_dword v5, v[0:1] glc
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; VI-SDAG-NEXT: s_waitcnt vmcnt(0)
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; VI-SDAG-NEXT: flat_load_dword v2, v[2:3] glc
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; VI-SDAG-NEXT: s_waitcnt vmcnt(0)
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; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
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; VI-SDAG-NEXT: v_add_u32_e32 v0, vcc, s0, v4
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; VI-SDAG-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-SDAG-NEXT: v_cvt_pk_i16_i32 v2, v5, v2
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; VI-SDAG-NEXT: flat_store_dword v[0:1], v2
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; VI-SDAG-NEXT: s_endpgm
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;
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; VI-GISEL-LABEL: v_cvt_pk_i16_i32:
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; VI-GISEL: ; %bb.0:
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; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
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; VI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 2, v0
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; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
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; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
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; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v4
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; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
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; VI-GISEL-NEXT: v_mov_b32_e32 v3, s5
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; VI-GISEL-NEXT: v_add_u32_e32 v2, vcc, v2, v4
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; VI-GISEL-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; VI-GISEL-NEXT: flat_load_dword v5, v[0:1] glc
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; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
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; VI-GISEL-NEXT: flat_load_dword v2, v[2:3] glc
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; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
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; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
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; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
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; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v4
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; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-GISEL-NEXT: v_cvt_pk_i16_i32 v2, v5, v2
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; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
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; VI-GISEL-NEXT: s_endpgm
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;
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; GFX9-LABEL: v_cvt_pk_i16_i32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: global_load_dword v2, v0, s[6:7] glc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_cvt_pk_i16_i32 v1, v1, v2
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; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
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; GFX9-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, ptr addrspace(1) %a.ptr, i64 %tid.ext
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%b.gep = getelementptr inbounds i32, ptr addrspace(1) %b.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext
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%a = load volatile i32, ptr addrspace(1) %a.gep
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%b = load volatile i32, ptr addrspace(1) %b.gep
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%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %a, i32 %b)
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%r = bitcast <2 x i16> %cvt to i32
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store i32 %r, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_cvt_pk_i16_i32_reg_imm(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
|
|
; SI-SDAG-LABEL: v_cvt_pk_i16_i32_reg_imm:
|
|
; SI-SDAG: ; %bb.0:
|
|
; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
|
|
; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
|
|
; SI-SDAG-NEXT: s_mov_b32 s6, 0
|
|
; SI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0
|
|
; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SI-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; SI-SDAG-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc
|
|
; SI-SDAG-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-SDAG-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; SI-SDAG-NEXT: v_cvt_pk_i16_i32_e64 v2, v2, 1
|
|
; SI-SDAG-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; SI-SDAG-NEXT: s_endpgm
|
|
;
|
|
; SI-GISEL-LABEL: v_cvt_pk_i16_i32_reg_imm:
|
|
; SI-GISEL: ; %bb.0:
|
|
; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
|
|
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
|
; SI-GISEL-NEXT: s_mov_b32 s6, 0
|
|
; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
|
|
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; SI-GISEL-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc
|
|
; SI-GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-GISEL-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; SI-GISEL-NEXT: v_cvt_pk_i16_i32_e64 v2, v2, 1
|
|
; SI-GISEL-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; SI-GISEL-NEXT: s_endpgm
|
|
;
|
|
; VI-SDAG-LABEL: v_cvt_pk_i16_i32_reg_imm:
|
|
; VI-SDAG: ; %bb.0:
|
|
; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; VI-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s3
|
|
; VI-SDAG-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; VI-SDAG-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-SDAG-NEXT: flat_load_dword v3, v[0:1] glc
|
|
; VI-SDAG-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
|
|
; VI-SDAG-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; VI-SDAG-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-SDAG-NEXT: v_cvt_pk_i16_i32 v2, v3, 1
|
|
; VI-SDAG-NEXT: flat_store_dword v[0:1], v2
|
|
; VI-SDAG-NEXT: s_endpgm
|
|
;
|
|
; VI-GISEL-LABEL: v_cvt_pk_i16_i32_reg_imm:
|
|
; VI-GISEL: ; %bb.0:
|
|
; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
|
|
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
|
|
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
|
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-GISEL-NEXT: flat_load_dword v3, v[0:1] glc
|
|
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
|
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
|
|
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
|
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-GISEL-NEXT: v_cvt_pk_i16_i32 v2, v3, 1
|
|
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
|
|
; VI-GISEL-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_cvt_pk_i16_i32_reg_imm:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_cvt_pk_i16_i32 v1, v1, 1
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%tid.ext = sext i32 %tid to i64
|
|
%a.gep = getelementptr inbounds i32, ptr addrspace(1) %a.ptr, i64 %tid.ext
|
|
%out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext
|
|
%a = load volatile i32, ptr addrspace(1) %a.gep
|
|
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %a, i32 1)
|
|
%r = bitcast <2 x i16> %cvt to i32
|
|
store i32 %r, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_cvt_pk_i16_i32_imm_reg(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
|
|
; SI-SDAG-LABEL: v_cvt_pk_i16_i32_imm_reg:
|
|
; SI-SDAG: ; %bb.0:
|
|
; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
|
|
; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
|
|
; SI-SDAG-NEXT: s_mov_b32 s6, 0
|
|
; SI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0
|
|
; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SI-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; SI-SDAG-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc
|
|
; SI-SDAG-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-SDAG-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; SI-SDAG-NEXT: v_cvt_pk_i16_i32_e32 v2, 1, v2
|
|
; SI-SDAG-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; SI-SDAG-NEXT: s_endpgm
|
|
;
|
|
; SI-GISEL-LABEL: v_cvt_pk_i16_i32_imm_reg:
|
|
; SI-GISEL: ; %bb.0:
|
|
; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
|
|
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
|
; SI-GISEL-NEXT: s_mov_b32 s6, 0
|
|
; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
|
|
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; SI-GISEL-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc
|
|
; SI-GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-GISEL-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; SI-GISEL-NEXT: v_cvt_pk_i16_i32_e32 v2, 1, v2
|
|
; SI-GISEL-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; SI-GISEL-NEXT: s_endpgm
|
|
;
|
|
; VI-SDAG-LABEL: v_cvt_pk_i16_i32_imm_reg:
|
|
; VI-SDAG: ; %bb.0:
|
|
; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; VI-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s3
|
|
; VI-SDAG-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; VI-SDAG-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-SDAG-NEXT: flat_load_dword v3, v[0:1] glc
|
|
; VI-SDAG-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
|
|
; VI-SDAG-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; VI-SDAG-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-SDAG-NEXT: v_cvt_pk_i16_i32 v2, 1, v3
|
|
; VI-SDAG-NEXT: flat_store_dword v[0:1], v2
|
|
; VI-SDAG-NEXT: s_endpgm
|
|
;
|
|
; VI-GISEL-LABEL: v_cvt_pk_i16_i32_imm_reg:
|
|
; VI-GISEL: ; %bb.0:
|
|
; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
|
|
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
|
|
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
|
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-GISEL-NEXT: flat_load_dword v3, v[0:1] glc
|
|
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
|
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
|
|
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
|
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-GISEL-NEXT: v_cvt_pk_i16_i32 v2, 1, v3
|
|
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
|
|
; VI-GISEL-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_cvt_pk_i16_i32_imm_reg:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_cvt_pk_i16_i32 v1, 1, v1
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%tid.ext = sext i32 %tid to i64
|
|
%a.gep = getelementptr inbounds i32, ptr addrspace(1) %a.ptr, i64 %tid.ext
|
|
%out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext
|
|
%a = load volatile i32, ptr addrspace(1) %a.gep
|
|
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 1, i32 %a)
|
|
%r = bitcast <2 x i16> %cvt to i32
|
|
store i32 %r, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
declare <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32, i32) #1
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind readnone }
|