derek.holloway
7502bf64a4
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216 lines
11 KiB
LLVM
216 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950,GFX950-SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950,GFX950-GISEL %s
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declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 %dst_sel)
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declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.bf16(i32 %old, <2 x bfloat> %src, i32 %seed, float %scale, i32 %dst_sel)
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declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f32(i32 %old, <2 x float> %src, i32 %seed, float %scale, i32 %dst_sel)
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_f16_dst_sel_0(ptr addrspace(1) %out, <2 x half> %src, i32 %seed, float %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_f16_dst_sel_0:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: global_load_dword v5, v[0:1], off
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f16 v6, v2, v3, v4
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; GFX950-NEXT: global_store_dword v[0:1], v6, off
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; GFX950-NEXT: s_endpgm
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%old = load i32, ptr addrspace(1) %out, align 4
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 0)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_f16_dst_sel_1(ptr addrspace(1) %out, <2 x half> %src, i32 %seed, float %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_f16_dst_sel_1:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: global_load_dword v5, v[0:1], off
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f16 v6, v2, v3, v4 op_sel:[0,0,1,0]
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; GFX950-NEXT: global_store_dword v[0:1], v6, off
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; GFX950-NEXT: s_endpgm
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%old = load i32, ptr addrspace(1) %out, align 4
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 1)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_f16_dst_sel_2(ptr addrspace(1) %out, <2 x half> %src, i32 %seed, float %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_f16_dst_sel_2:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: global_load_dword v5, v[0:1], off
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f16 v6, v2, v3, v4 op_sel:[0,0,0,1]
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; GFX950-NEXT: global_store_dword v[0:1], v6, off
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; GFX950-NEXT: s_endpgm
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%old = load i32, ptr addrspace(1) %out, align 4
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 2)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_f16_dst_sel_3(ptr addrspace(1) %out, <2 x half> %src, i32 %seed, float %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_f16_dst_sel_3:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: global_load_dword v5, v[0:1], off
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f16 v6, v2, v3, v4 op_sel:[0,0,1,1]
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; GFX950-NEXT: global_store_dword v[0:1], v6, off
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; GFX950-NEXT: s_endpgm
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%old = load i32, ptr addrspace(1) %out, align 4
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 3)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_bf16_dst_sel_0(ptr addrspace(1) %out, <2 x bfloat> %src, i32 %seed, float %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_bf16_dst_sel_0:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: global_load_dword v5, v[0:1], off
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_bf16 v6, v2, v3, v4
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; GFX950-NEXT: global_store_dword v[0:1], v6, off
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; GFX950-NEXT: s_endpgm
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%old = load i32, ptr addrspace(1) %out, align 4
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.bf16(i32 %old, <2 x bfloat> %src, i32 %seed, float %scale, i32 0)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_bf16_dst_sel_1(ptr addrspace(1) %out, <2 x bfloat> %src, i32 %seed, float %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_bf16_dst_sel_1:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: global_load_dword v5, v[0:1], off
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_bf16 v6, v2, v3, v4 op_sel:[0,0,1,0]
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; GFX950-NEXT: global_store_dword v[0:1], v6, off
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; GFX950-NEXT: s_endpgm
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%old = load i32, ptr addrspace(1) %out, align 4
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.bf16(i32 %old, <2 x bfloat> %src, i32 %seed, float %scale, i32 1)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_bf16_dst_sel_2(ptr addrspace(1) %out, <2 x bfloat> %src, i32 %seed, float %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_bf16_dst_sel_2:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: global_load_dword v5, v[0:1], off
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_bf16 v6, v2, v3, v4 op_sel:[0,0,0,1]
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; GFX950-NEXT: global_store_dword v[0:1], v6, off
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; GFX950-NEXT: s_endpgm
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%old = load i32, ptr addrspace(1) %out, align 4
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.bf16(i32 %old, <2 x bfloat> %src, i32 %seed, float %scale, i32 2)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_bf16_dst_sel_3(ptr addrspace(1) %out, <2 x bfloat> %src, i32 %seed, float %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_bf16_dst_sel_3:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: global_load_dword v5, v[0:1], off
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_bf16 v6, v2, v3, v4 op_sel:[0,0,1,1]
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; GFX950-NEXT: global_store_dword v[0:1], v6, off
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; GFX950-NEXT: s_endpgm
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%old = load i32, ptr addrspace(1) %out, align 4
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.bf16(i32 %old, <2 x bfloat> %src, i32 %seed, float %scale, i32 3)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_f32_dst_sel_0(ptr addrspace(1) %out, <2 x float> %src, i32 %seed, float %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_f32_dst_sel_0:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: global_load_dword v6, v[0:1], off
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f32 v7, v[2:3], v4, v5
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; GFX950-NEXT: global_store_dword v[0:1], v7, off
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; GFX950-NEXT: s_endpgm
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%old = load i32, ptr addrspace(1) %out, align 4
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f32(i32 %old, <2 x float> %src, i32 %seed, float %scale, i32 0)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_f32_dst_sel_1(ptr addrspace(1) %out, <2 x float> %src, i32 %seed, float %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_f32_dst_sel_1:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: global_load_dword v6, v[0:1], off
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f32 v7, v[2:3], v4, v5 op_sel:[0,0,1,0]
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; GFX950-NEXT: global_store_dword v[0:1], v7, off
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; GFX950-NEXT: s_endpgm
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%old = load i32, ptr addrspace(1) %out, align 4
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f32(i32 %old, <2 x float> %src, i32 %seed, float %scale, i32 1)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_f32_dst_sel_2(ptr addrspace(1) %out, <2 x float> %src, i32 %seed, float %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_f32_dst_sel_2:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: global_load_dword v6, v[0:1], off
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f32 v7, v[2:3], v4, v5 op_sel:[0,0,0,1]
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; GFX950-NEXT: global_store_dword v[0:1], v7, off
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; GFX950-NEXT: s_endpgm
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%old = load i32, ptr addrspace(1) %out, align 4
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f32(i32 %old, <2 x float> %src, i32 %seed, float %scale, i32 2)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_f32_dst_sel_3(ptr addrspace(1) %out, <2 x float> %src, i32 %seed, float %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_f32_dst_sel_3:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: global_load_dword v6, v[0:1], off
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f32 v7, v[2:3], v4, v5 op_sel:[0,0,1,1]
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; GFX950-NEXT: global_store_dword v[0:1], v7, off
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; GFX950-NEXT: s_endpgm
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%old = load i32, ptr addrspace(1) %out, align 4
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f32(i32 %old, <2 x float> %src, i32 %seed, float %scale, i32 3)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_f16_uni(ptr addrspace(1) %out, i32 inreg %old, <2 x half> inreg %src, i32 inreg %seed, float inreg %scale) {
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; GFX950-LABEL: test_scalef32_sr_pk_fp4_f16_uni:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: v_mov_b32_e32 v2, s0
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; GFX950-NEXT: v_mov_b32_e32 v3, s2
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; GFX950-NEXT: v_mov_b32_e32 v4, s3
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; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f16 v5, s1, v3, v4
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; GFX950-NEXT: global_store_dword v[0:1], v5, off
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; GFX950-NEXT: s_endpgm
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 0)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk_fp4_f32_uni(ptr addrspace(1) %out, i32 inreg %old, <2 x float> inreg %src, i32 inreg %seed, float inreg %scale) {
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; GFX950-SDAG-LABEL: test_scalef32_sr_pk_fp4_f32_uni:
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; GFX950-SDAG: ; %bb.0:
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; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s1
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; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s2
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; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s0
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; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s4
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; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk_fp4_f32 v6, v[2:3], s3, v5
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; GFX950-SDAG-NEXT: global_store_dword v[0:1], v6, off
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; GFX950-SDAG-NEXT: s_endpgm
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;
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; GFX950-GISEL-LABEL: test_scalef32_sr_pk_fp4_f32_uni:
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; GFX950-GISEL: ; %bb.0:
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; GFX950-GISEL-NEXT: s_mov_b32 s6, s1
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; GFX950-GISEL-NEXT: s_mov_b32 s7, s2
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; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, s0
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; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
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; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, s4
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; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk_fp4_f32 v6, v[2:3], s3, v5
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; GFX950-GISEL-NEXT: global_store_dword v[0:1], v6, off
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; GFX950-GISEL-NEXT: s_endpgm
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%cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f32(i32 %old, <2 x float> %src, i32 %seed, float %scale, i32 0)
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store i32 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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