derek.holloway
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103 lines
4.4 KiB
LLVM
103 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GISEL %s
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declare i64 @llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64(ptr addrspace(3), i64)
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define void @test_ds_atomic_barrier_arrive_rtn_b64(i64 %data, ptr addrspace(3) %bar, ptr %out) {
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; SDAG-LABEL: test_ds_atomic_barrier_arrive_rtn_b64:
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; SDAG: ; %bb.0: ; %entry
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; SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
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; SDAG-NEXT: s_wait_kmcnt 0x0
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; SDAG-NEXT: ds_atomic_barrier_arrive_rtn_b64 v[0:1], v2, v[0:1]
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; SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
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; SDAG-NEXT: s_wait_dscnt 0x0
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; SDAG-NEXT: flat_store_b64 v[4:5], v[0:1]
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; SDAG-NEXT: s_wait_dscnt 0x0
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; SDAG-NEXT: s_set_pc_i64 s[30:31]
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;
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; GISEL-LABEL: test_ds_atomic_barrier_arrive_rtn_b64:
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; GISEL: ; %bb.0: ; %entry
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; GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GISEL-NEXT: s_wait_kmcnt 0x0
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; GISEL-NEXT: ds_atomic_barrier_arrive_rtn_b64 v[0:1], v2, v[0:1]
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; GISEL-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
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; GISEL-NEXT: s_wait_dscnt 0x0
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; GISEL-NEXT: flat_store_b64 v[6:7], v[0:1]
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; GISEL-NEXT: s_wait_dscnt 0x0
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; GISEL-NEXT: s_set_pc_i64 s[30:31]
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entry:
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%ret = call i64 @llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64(ptr addrspace(3) %bar, i64 %data)
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store i64 %ret, ptr %out
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ret void
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}
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define void @test_ds_atomic_barrier_arrive_rtn_b64_off(ptr addrspace(3) %in, ptr %out) {
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; SDAG-LABEL: test_ds_atomic_barrier_arrive_rtn_b64_off:
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; SDAG: ; %bb.0: ; %entry
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; SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
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; SDAG-NEXT: s_wait_kmcnt 0x0
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; SDAG-NEXT: v_mov_b64_e32 v[4:5], 0x200
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; SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
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; SDAG-NEXT: ds_atomic_barrier_arrive_rtn_b64 v[0:1], v0, v[4:5] offset:8184
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; SDAG-NEXT: s_wait_dscnt 0x0
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; SDAG-NEXT: flat_store_b64 v[2:3], v[0:1]
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; SDAG-NEXT: s_wait_dscnt 0x0
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; SDAG-NEXT: s_set_pc_i64 s[30:31]
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;
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; GISEL-LABEL: test_ds_atomic_barrier_arrive_rtn_b64_off:
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; GISEL: ; %bb.0: ; %entry
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; GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GISEL-NEXT: s_wait_kmcnt 0x0
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; GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
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; GISEL-NEXT: v_mov_b64_e32 v[2:3], 0x200
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; GISEL-NEXT: ds_atomic_barrier_arrive_rtn_b64 v[0:1], v0, v[2:3] offset:8184
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; GISEL-NEXT: s_wait_dscnt 0x0
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; GISEL-NEXT: flat_store_b64 v[4:5], v[0:1]
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; GISEL-NEXT: s_wait_dscnt 0x0
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; GISEL-NEXT: s_set_pc_i64 s[30:31]
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entry:
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%bar = getelementptr i64, ptr addrspace(3) %in, i32 1023
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%ret = call i64 @llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64(ptr addrspace(3) %bar, i64 512)
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store i64 %ret, ptr %out
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ret void
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}
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define amdgpu_ps void @test_ds_atomic_barrier_arrive_rtn_b64_ss(ptr addrspace(3) inreg %bar, i64 inreg %data, ptr inreg %out) {
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; SDAG-LABEL: test_ds_atomic_barrier_arrive_rtn_b64_ss:
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; SDAG: ; %bb.0: ; %entry
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; SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; SDAG-NEXT: v_nop
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; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s2
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; SDAG-NEXT: v_mov_b32_e32 v2, s0
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; SDAG-NEXT: s_mov_b32 s5, s4
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; SDAG-NEXT: s_mov_b32 s4, s3
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; SDAG-NEXT: ds_atomic_barrier_arrive_rtn_b64 v[0:1], v2, v[0:1]
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; SDAG-NEXT: v_mov_b32_e32 v2, 0
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; SDAG-NEXT: s_wait_dscnt 0x0
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; SDAG-NEXT: flat_store_b64 v2, v[0:1], s[4:5]
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; SDAG-NEXT: s_endpgm
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;
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; GISEL-LABEL: test_ds_atomic_barrier_arrive_rtn_b64_ss:
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; GISEL: ; %bb.0: ; %entry
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; GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GISEL-NEXT: v_nop
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; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GISEL-NEXT: s_mov_b32 s6, s1
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; GISEL-NEXT: s_mov_b32 s7, s2
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; GISEL-NEXT: v_mov_b32_e32 v2, s0
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; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
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; GISEL-NEXT: s_mov_b32 s2, s3
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; GISEL-NEXT: s_mov_b32 s3, s4
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; GISEL-NEXT: ds_atomic_barrier_arrive_rtn_b64 v[0:1], v2, v[0:1]
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; GISEL-NEXT: v_mov_b32_e32 v2, 0
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; GISEL-NEXT: s_wait_dscnt 0x0
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; GISEL-NEXT: flat_store_b64 v2, v[0:1], s[2:3]
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; GISEL-NEXT: s_endpgm
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entry:
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%ret = call i64 @llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64(ptr addrspace(3) %bar, i64 %data)
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store i64 %ret, ptr %out
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ret void
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}
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