derek.holloway
7502bf64a4
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27 lines
1.4 KiB
LLVM
27 lines
1.4 KiB
LLVM
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN %s
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; GCN-LABEL: {{^}}ds_ordered_add:
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; GCN-DAG: v_{{(dual_)?}}mov_b32{{(_e32)?}} v[[INCR:[0-9]+]], 31
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; GCN-DAG: s_mov_b32 m0,
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; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
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define amdgpu_kernel void @ds_ordered_add(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {
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%val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 16777217, i1 true, i1 true)
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}ds_ordered_add_4dw:
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; GCN-DAG: v_{{(dual_)?}}mov_b32{{(_e32)?}} v[[INCR:[0-9]+]], 31
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; GCN-DAG: s_mov_b32 m0,
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; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:49924 gds
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define amdgpu_kernel void @ds_ordered_add_4dw(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {
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%val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 67108865, i1 true, i1 true)
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) nocapture, i32, i32, i32, i1, i32, i1, i1)
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