derek.holloway
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235 lines
7.9 KiB
LLVM
235 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GISEL %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
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define float @v_exp2_f32(float %src) {
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; GCN-LABEL: v_exp2_f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_exp_f32_e32 v0, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_exp2_f32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_exp_f32_e32 v0, v0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_exp2_f32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_exp_f32_e32 v0, v0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%exp2 = call float @llvm.amdgcn.exp2.f32(float %src)
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ret float %exp2
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}
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define float @v_exp2_f32_uniform(float inreg %src) {
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; GCN-LABEL: v_exp2_f32_uniform:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_exp_f32_e32 v0, s16
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_exp2_f32_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_exp_f32_e32 v0, s0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_exp2_f32_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_s_exp_f32 s0, s0
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; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
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; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%exp2 = call float @llvm.amdgcn.exp2.f32(float %src)
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ret float %exp2
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}
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define float @v_fabs_exp2_f32(float %src) {
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; GCN-LABEL: v_fabs_exp2_f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_exp_f32_e64 v0, |v0|
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_fabs_exp2_f32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_exp_f32_e64 v0, |v0|
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_fabs_exp2_f32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_exp_f32_e64 v0, |v0|
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%fabs.src = call float @llvm.fabs.f32(float %src)
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%exp2 = call float @llvm.amdgcn.exp2.f32(float %fabs.src)
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ret float %exp2
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}
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define float @v_fneg_fabs_exp2_f32(float %src) {
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; GCN-LABEL: v_fneg_fabs_exp2_f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_exp_f32_e64 v0, -|v0|
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_fneg_fabs_exp2_f32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_exp_f32_e64 v0, -|v0|
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_fneg_fabs_exp2_f32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_exp_f32_e64 v0, -|v0|
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%fabs.src = call float @llvm.fabs.f32(float %src)
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%neg.fabs.src = fneg float %fabs.src
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%exp2 = call float @llvm.amdgcn.exp2.f32(float %neg.fabs.src)
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ret float %exp2
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}
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define half @v_exp2_f16(half %src) {
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; GCN-LABEL: v_exp2_f16:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_exp_f16_e32 v0, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_exp2_f16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_exp_f16_e32 v0.l, v0.l
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_exp2_f16:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_exp_f16_e32 v0.l, v0.l
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%exp2 = call half @llvm.amdgcn.exp2.f16(half %src)
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ret half %exp2
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}
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define half @v_exp2_f16_uniform(half inreg %src) {
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; GCN-LABEL: v_exp2_f16_uniform:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_exp_f16_e32 v0, s16
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_exp2_f16_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_exp_f16_e32 v0.l, s0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_exp2_f16_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_s_exp_f16 s0, s0
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; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
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; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%exp2 = call half @llvm.amdgcn.exp2.f16(half %src)
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ret half %exp2
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}
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define half @v_fabs_exp2_f16(half %src) {
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; GCN-LABEL: v_fabs_exp2_f16:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_exp_f16_e64 v0, |v0|
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_fabs_exp2_f16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_exp_f16_e64 v0.l, |v0.l|
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_fabs_exp2_f16:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_exp_f16_e64 v0.l, |v0.l|
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%fabs.src = call half @llvm.fabs.f16(half %src)
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%exp2 = call half @llvm.amdgcn.exp2.f16(half %fabs.src)
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ret half %exp2
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}
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define half @v_fneg_fabs_exp2_f16(half %src) {
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; GCN-LABEL: v_fneg_fabs_exp2_f16:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_exp_f16_e64 v0, -|v0|
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_fneg_fabs_exp2_f16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_exp_f16_e64 v0.l, -|v0.l|
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_fneg_fabs_exp2_f16:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_exp_f16_e64 v0.l, -|v0.l|
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%fabs.src = call half @llvm.fabs.f16(half %src)
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%neg.fabs.src = fneg half %fabs.src
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%exp2 = call half @llvm.amdgcn.exp2.f16(half %neg.fabs.src)
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ret half %exp2
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}
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declare half @llvm.amdgcn.exp2.f16(half) #0
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declare float @llvm.amdgcn.exp2.f32(float) #0
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declare float @llvm.fabs.f32(float) #0
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declare half @llvm.fabs.f16(half) #0
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attributes #0 = { nounwind readnone speculatable willreturn }
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; GISEL: {{.*}}
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; SDAG: {{.*}}
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