derek.holloway
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107 lines
4.8 KiB
LLVM
107 lines
4.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_fmed3:
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; GCN: v_med3_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @test_fmed3(ptr addrspace(1) %out, float %src0, float %src1, float %src2) #1 {
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%med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)
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store float %med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_fmed3_srcmods:
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; GCN: v_med3_f32 v{{[0-9]+}}, -s{{[0-9]+}}, |v{{[0-9]+}}|, -|v{{[0-9]+}}|
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define amdgpu_kernel void @test_fmed3_srcmods(ptr addrspace(1) %out, float %src0, float %src1, float %src2) #1 {
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%src0.fneg = fsub float -0.0, %src0
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%src1.fabs = call float @llvm.fabs.f32(float %src1)
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%src2.fabs = call float @llvm.fabs.f32(float %src2)
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%src2.fneg.fabs = fsub float -0.0, %src2.fabs
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%med3 = call float @llvm.amdgcn.fmed3.f32(float %src0.fneg, float %src1.fabs, float %src2.fneg.fabs)
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store float %med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_fneg_fmed3:
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; GCN: v_med3_f32 v{{[0-9]+}}, -s{{[0-9]+}}, -v{{[0-9]+}}, -v{{[0-9]+}}
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define amdgpu_kernel void @test_fneg_fmed3(ptr addrspace(1) %out, float %src0, float %src1, float %src2) #1 {
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%med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)
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%neg.med3 = fsub float -0.0, %med3
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store float %neg.med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_fneg_fmed3_multi_use:
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; GCN: v_med3_f32 [[MED3:v[0-9]+]], -s{{[0-9]+}}, -v{{[0-9]+}}, -v{{[0-9]+}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, -4.0, [[MED3]]
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define amdgpu_kernel void @test_fneg_fmed3_multi_use(ptr addrspace(1) %out, float %src0, float %src1, float %src2) #1 {
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%med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)
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%neg.med3 = fsub float -0.0, %med3
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%med3.user = fmul float %med3, 4.0
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store volatile float %med3.user, ptr addrspace(1) %out
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store volatile float %neg.med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_fabs_fmed3:
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; GCN: v_med3_f32 [[MED3:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 0x7fffffff, [[MED3]]
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define amdgpu_kernel void @test_fabs_fmed3(ptr addrspace(1) %out, float %src0, float %src1, float %src2) #1 {
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%med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)
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%fabs.med3 = call float @llvm.fabs.f32(float %med3)
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store float %fabs.med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_fneg_fmed3_rr_0:
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; GCN: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 1
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; GCN: v_med3_f32 v{{[0-9]+}}, -s{{[0-9]+}}, -v{{[0-9]+}}, [[NEG0]]
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define amdgpu_kernel void @test_fneg_fmed3_rr_0(ptr addrspace(1) %out, float %src0, float %src1) #1 {
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%med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float 0.0)
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%neg.med3 = fsub float -0.0, %med3
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store float %neg.med3, ptr addrspace(1) %out
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ret void
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}
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; FIXME: Worse off from folding this
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; GCN-LABEL: {{^}}test_fneg_fmed3_rr_0_foldable_user:
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; GCN: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 1
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; GCN: v_med3_f32 [[MED3:v[0-9]+]], -s{{[0-9]+}}, -v{{[0-9]+}}, [[NEG0]]
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[MED3]]
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define amdgpu_kernel void @test_fneg_fmed3_rr_0_foldable_user(ptr addrspace(1) %out, float %src0, float %src1, float %mul.arg) #1 {
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%med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float 0.0)
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%neg.med3 = fsub float -0.0, %med3
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%mul = fmul float %neg.med3, %mul.arg
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store float %mul, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_fneg_fmed3_r_inv2pi_0:
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; GCN-DAG: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 1
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; GCN-DAG: v_mov_b32_e32 [[NEG_INV:v[0-9]+]], 0xbe22f983
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; GCN: v_med3_f32 v{{[0-9]+}}, -s{{[0-9]+}}, [[NEG_INV]], [[NEG0]]
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define amdgpu_kernel void @test_fneg_fmed3_r_inv2pi_0(ptr addrspace(1) %out, float %src0) #1 {
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%med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float 0x3FC45F3060000000, float 0.0)
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%neg.med3 = fsub float -0.0, %med3
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store float %neg.med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_fneg_fmed3_r_inv2pi_0_foldable_user:
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; GCN-DAG: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 1
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; GCN-DAG: v_mov_b32_e32 [[NEG_INV:v[0-9]+]], 0xbe22f983
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; GCN: v_med3_f32 [[MED3:v[0-9]+]], -s{{[0-9]+}}, [[NEG_INV]], [[NEG0]]
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[MED3]]
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define amdgpu_kernel void @test_fneg_fmed3_r_inv2pi_0_foldable_user(ptr addrspace(1) %out, float %src0, float %mul.arg) #1 {
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%med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float 0x3FC45F3060000000, float 0.0)
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%neg.med3 = fsub float -0.0, %med3
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%mul = fmul float %neg.med3, %mul.arg
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store float %mul, ptr addrspace(1) %out
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ret void
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}
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declare float @llvm.amdgcn.fmed3.f32(float, float, float) #0
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declare float @llvm.fabs.f32(float) #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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