derek.holloway
7502bf64a4
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169 lines
7.7 KiB
LLVM
169 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -o - %s | FileCheck -check-prefix=GCN %s
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define amdgpu_kernel void @MFMAExpInterleave(ptr addrspace(1) %out0, ptr addrspace(1) %out1, float %in0, <4 x float> %in1) {
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; GCN-LABEL: MFMAExpInterleave:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s6, s[4:5], 0x10
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x20
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; GCN-NEXT: v_mov_b32_e32 v5, 0x3fb8aa3b
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; GCN-NEXT: v_mov_b32_e32 v4, 1.0
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; GCN-NEXT: s_mov_b32 s7, 0x42b17218
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mul_f32_e32 v6, s6, v5
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; GCN-NEXT: v_rndne_f32_e32 v7, v6
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; GCN-NEXT: v_sub_f32_e32 v8, v6, v7
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; GCN-NEXT: v_fma_f32 v5, s6, v5, -v6
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; GCN-NEXT: v_mov_b32_e32 v6, 0x32a5705f
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; GCN-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
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; GCN-NEXT: v_fmac_f32_e32 v5, s6, v6
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; GCN-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
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; GCN-NEXT: v_add_f32_e32 v5, v8, v5
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; GCN-NEXT: v_cvt_i32_f32_e32 v6, v7
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; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
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; GCN-NEXT: v_exp_f32_e32 v5, v5
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; GCN-NEXT: s_mov_b32 s0, 0x3fb8aa3b
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; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
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; GCN-NEXT: ; iglp_opt mask(0x00000003)
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; GCN-NEXT: v_ldexp_f32 v5, v5, v6
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; GCN-NEXT: v_mov_b32_e32 v6, 0xc2ce8ed0
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; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s6, v6
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; GCN-NEXT: v_mov_b32_e32 v6, 0x42b17218
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
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; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v6
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; GCN-NEXT: v_mov_b32_e32 v6, 0x7f800000
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; GCN-NEXT: s_mov_b32 s6, 0xc2ce8ed0
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; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
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; GCN-NEXT: v_mul_f32_e32 v7, 0x3fb8aa3b, v5
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; GCN-NEXT: v_fma_f32 v8, v5, s0, -v7
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; GCN-NEXT: v_rndne_f32_e32 v9, v7
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; GCN-NEXT: v_fmac_f32_e32 v8, 0x32a5705f, v5
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; GCN-NEXT: v_sub_f32_e32 v7, v7, v9
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; GCN-NEXT: v_add_f32_e32 v7, v7, v8
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; GCN-NEXT: v_exp_f32_e32 v7, v7
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; GCN-NEXT: v_cvt_i32_f32_e32 v8, v9
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; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v5
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; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
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; GCN-NEXT: v_ldexp_f32 v7, v7, v8
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; GCN-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
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; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v5
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
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; GCN-NEXT: v_mul_f32_e32 v7, 0x3fb8aa3b, v5
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; GCN-NEXT: v_fma_f32 v8, v5, s0, -v7
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; GCN-NEXT: v_rndne_f32_e32 v9, v7
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; GCN-NEXT: v_fmac_f32_e32 v8, 0x32a5705f, v5
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; GCN-NEXT: v_sub_f32_e32 v7, v7, v9
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; GCN-NEXT: v_add_f32_e32 v7, v7, v8
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; GCN-NEXT: v_exp_f32_e32 v7, v7
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; GCN-NEXT: v_cvt_i32_f32_e32 v8, v9
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; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v5
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; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
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; GCN-NEXT: v_ldexp_f32 v7, v7, v8
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; GCN-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
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; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v5
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
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; GCN-NEXT: v_mul_f32_e32 v7, 0x3fb8aa3b, v5
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; GCN-NEXT: v_fma_f32 v8, v5, s0, -v7
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; GCN-NEXT: v_rndne_f32_e32 v9, v7
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; GCN-NEXT: v_fmac_f32_e32 v8, 0x32a5705f, v5
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; GCN-NEXT: v_sub_f32_e32 v7, v7, v9
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; GCN-NEXT: v_add_f32_e32 v7, v7, v8
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; GCN-NEXT: v_exp_f32_e32 v7, v7
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; GCN-NEXT: v_cvt_i32_f32_e32 v8, v9
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; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v5
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; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
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; GCN-NEXT: v_ldexp_f32 v7, v7, v8
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; GCN-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
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; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v5
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
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; GCN-NEXT: v_mul_f32_e32 v7, 0x3fb8aa3b, v5
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; GCN-NEXT: v_fma_f32 v8, v5, s0, -v7
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; GCN-NEXT: v_rndne_f32_e32 v9, v7
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; GCN-NEXT: v_fmac_f32_e32 v8, 0x32a5705f, v5
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; GCN-NEXT: v_sub_f32_e32 v7, v7, v9
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; GCN-NEXT: v_add_f32_e32 v7, v7, v8
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; GCN-NEXT: v_exp_f32_e32 v7, v7
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; GCN-NEXT: v_cvt_i32_f32_e32 v8, v9
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; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v5
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; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
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; GCN-NEXT: v_ldexp_f32 v7, v7, v8
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; GCN-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
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; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v5
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
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; GCN-NEXT: v_mul_f32_e32 v7, 0x3fb8aa3b, v5
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; GCN-NEXT: v_fma_f32 v8, v5, s0, -v7
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; GCN-NEXT: v_rndne_f32_e32 v9, v7
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; GCN-NEXT: v_fmac_f32_e32 v8, 0x32a5705f, v5
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; GCN-NEXT: v_sub_f32_e32 v7, v7, v9
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; GCN-NEXT: v_add_f32_e32 v7, v7, v8
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; GCN-NEXT: v_exp_f32_e32 v7, v7
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; GCN-NEXT: v_cvt_i32_f32_e32 v8, v9
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; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v5
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; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
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; GCN-NEXT: v_ldexp_f32 v7, v7, v8
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; GCN-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
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; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v5
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
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; GCN-NEXT: v_mul_f32_e32 v7, 0x3fb8aa3b, v5
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; GCN-NEXT: v_fma_f32 v8, v5, s0, -v7
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; GCN-NEXT: v_rndne_f32_e32 v9, v7
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; GCN-NEXT: v_fmac_f32_e32 v8, 0x32a5705f, v5
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; GCN-NEXT: v_sub_f32_e32 v7, v7, v9
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; GCN-NEXT: v_add_f32_e32 v7, v7, v8
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; GCN-NEXT: v_exp_f32_e32 v7, v7
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; GCN-NEXT: v_cvt_i32_f32_e32 v8, v9
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; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
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; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v5
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; GCN-NEXT: v_ldexp_f32 v4, v7, v8
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
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; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v5
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
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; GCN-NEXT: v_mul_f32_e32 v5, 0x3fb8aa3b, v4
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; GCN-NEXT: v_fma_f32 v7, v4, s0, -v5
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; GCN-NEXT: v_rndne_f32_e32 v8, v5
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; GCN-NEXT: v_fmac_f32_e32 v7, 0x32a5705f, v4
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; GCN-NEXT: v_sub_f32_e32 v5, v5, v8
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; GCN-NEXT: v_add_f32_e32 v5, v5, v7
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; GCN-NEXT: v_exp_f32_e32 v5, v5
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; GCN-NEXT: v_cvt_i32_f32_e32 v7, v8
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v4
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; GCN-NEXT: v_mov_b32_e32 v8, 0
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; GCN-NEXT: v_ldexp_f32 v5, v5, v7
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; GCN-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
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; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v4
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
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; GCN-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc
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; GCN-NEXT: global_store_dword v8, v4, s[2:3]
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; GCN-NEXT: s_endpgm
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%mai0 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %in1, i32 0, i32 0, i32 0)
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%mai1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %mai0, i32 0, i32 0, i32 0)
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%mai2 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %mai1, i32 0, i32 0, i32 0)
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%mai3 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %mai2, i32 0, i32 0, i32 0)
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%mai4 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %mai3, i32 0, i32 0, i32 0)
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%mai5 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %mai4, i32 0, i32 0, i32 0)
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%mai6 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %mai5, i32 0, i32 0, i32 0)
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%mai7 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %mai6, i32 0, i32 0, i32 0)
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%exp0 = call float @llvm.exp.f32(float %in0)
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%exp1 = call float @llvm.exp.f32(float %exp0)
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%exp2 = call float @llvm.exp.f32(float %exp1)
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%exp3 = call float @llvm.exp.f32(float %exp2)
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%exp4 = call float @llvm.exp.f32(float %exp3)
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%exp5 = call float @llvm.exp.f32(float %exp4)
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%exp6 = call float @llvm.exp.f32(float %exp5)
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%exp7 = call float @llvm.exp.f32(float %exp6)
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store <4 x float> %mai7, ptr addrspace(1) %out0
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store float %exp7, ptr addrspace(1) %out1
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tail call void @llvm.amdgcn.iglp.opt(i32 3)
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ret void
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}
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