derek.holloway
7502bf64a4
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1156 lines
51 KiB
LLVM
1156 lines
51 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -amdgpu-mfma-vgpr-form=0 < %s | FileCheck -enable-var-scope --check-prefix=AGPR %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -enable-var-scope --check-prefix=VGPR %s
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; FIXME: bfloat vector arguments are broken in globalisel.
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; https://github.com/llvm/llvm-project/issues/77055
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declare <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat>, <8 x bfloat>, <16 x float>, i32 immarg, i32 immarg, i32 immarg)
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; --------------------------------------------------------------------
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; llvm.amdgcn.mfma.f32.32x32x16.bf16
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; --------------------------------------------------------------------
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define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2) #1 {
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; GCN-LABEL: test_mfma_f32_32x32x16_bf16:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
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; GCN-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
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; GCN-NEXT: v_mov_b64_e32 v[0:1], 48
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; GCN-NEXT: v_mov_b64_e32 v[2:3], 32
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; GCN-NEXT: v_mov_b64_e32 v[4:5], 16
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b64_e32 v[8:9], s[24:25]
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; GCN-NEXT: v_mov_b64_e32 v[10:11], s[26:27]
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; GCN-NEXT: v_mov_b64_e32 v[12:13], s[28:29]
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; GCN-NEXT: v_accvgpr_write_b32 a0, s8
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; GCN-NEXT: v_mov_b64_e32 v[14:15], s[30:31]
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; GCN-NEXT: v_accvgpr_write_b32 a1, s9
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; GCN-NEXT: v_accvgpr_write_b32 a2, s10
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; GCN-NEXT: v_accvgpr_write_b32 a3, s11
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; GCN-NEXT: v_accvgpr_write_b32 a4, s12
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; GCN-NEXT: v_accvgpr_write_b32 a5, s13
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; GCN-NEXT: v_accvgpr_write_b32 a6, s14
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; GCN-NEXT: v_accvgpr_write_b32 a7, s15
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; GCN-NEXT: v_accvgpr_write_b32 a8, s16
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; GCN-NEXT: v_accvgpr_write_b32 a9, s17
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; GCN-NEXT: v_accvgpr_write_b32 a10, s18
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; GCN-NEXT: v_accvgpr_write_b32 a11, s19
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; GCN-NEXT: v_accvgpr_write_b32 a12, s20
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; GCN-NEXT: v_accvgpr_write_b32 a13, s21
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; GCN-NEXT: v_accvgpr_write_b32 a14, s22
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; GCN-NEXT: v_accvgpr_write_b32 a15, s23
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; GCN-NEXT: v_mov_b32_e32 v16, s16
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; GCN-NEXT: v_mov_b32_e32 v17, s17
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; GCN-NEXT: v_mfma_f32_32x32x16_bf16 a[16:31], v[8:11], v[12:15], a[0:15]
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; GCN-NEXT: v_mov_b32_e32 v18, s18
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; GCN-NEXT: v_mov_b32_e32 v19, s19
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; GCN-NEXT: v_mov_b32_e32 v8, s20
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; GCN-NEXT: v_mov_b32_e32 v9, s21
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; GCN-NEXT: v_mov_b32_e32 v10, s22
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; GCN-NEXT: v_mov_b32_e32 v11, s23
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; GCN-NEXT: v_mov_b64_e32 v[6:7], 0
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; GCN-NEXT: s_nop 4
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; GCN-NEXT: global_store_dwordx4 v[0:1], a[28:31], off sc0 sc1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: global_store_dwordx4 v[2:3], a[24:27], off sc0 sc1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: global_store_dwordx4 v[4:5], a[20:23], off sc0 sc1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: global_store_dwordx4 v[6:7], a[16:19], off sc0 sc1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: global_store_dwordx4 v[2:3], v[16:19], off sc0 sc1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: global_store_dwordx4 v[0:1], v[8:11], off sc0 sc1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s8
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; GCN-NEXT: v_mov_b32_e32 v1, s9
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; GCN-NEXT: v_mov_b32_e32 v2, s10
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; GCN-NEXT: v_mov_b32_e32 v3, s11
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; GCN-NEXT: global_store_dwordx4 v[6:7], v[0:3], off sc0 sc1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: v_mov_b32_e32 v0, s12
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; GCN-NEXT: v_mov_b32_e32 v1, s13
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; GCN-NEXT: v_mov_b32_e32 v2, s14
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; GCN-NEXT: v_mov_b32_e32 v3, s15
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; GCN-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_endpgm
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;
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; AGPR-LABEL: test_mfma_f32_32x32x16_bf16:
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; AGPR: ; %bb.0:
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; AGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
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; AGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
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; AGPR-NEXT: v_mov_b64_e32 v[0:1], 48
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; AGPR-NEXT: v_mov_b64_e32 v[2:3], 32
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; AGPR-NEXT: v_mov_b64_e32 v[4:5], 16
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; AGPR-NEXT: s_waitcnt lgkmcnt(0)
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; AGPR-NEXT: v_mov_b64_e32 v[8:9], s[24:25]
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; AGPR-NEXT: v_mov_b64_e32 v[10:11], s[26:27]
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; AGPR-NEXT: v_mov_b64_e32 v[12:13], s[28:29]
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; AGPR-NEXT: v_accvgpr_write_b32 a0, s8
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; AGPR-NEXT: v_mov_b64_e32 v[14:15], s[30:31]
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; AGPR-NEXT: v_accvgpr_write_b32 a1, s9
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; AGPR-NEXT: v_accvgpr_write_b32 a2, s10
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; AGPR-NEXT: v_accvgpr_write_b32 a3, s11
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; AGPR-NEXT: v_accvgpr_write_b32 a4, s12
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; AGPR-NEXT: v_accvgpr_write_b32 a5, s13
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; AGPR-NEXT: v_accvgpr_write_b32 a6, s14
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; AGPR-NEXT: v_accvgpr_write_b32 a7, s15
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; AGPR-NEXT: v_accvgpr_write_b32 a8, s16
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; AGPR-NEXT: v_accvgpr_write_b32 a9, s17
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; AGPR-NEXT: v_accvgpr_write_b32 a10, s18
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; AGPR-NEXT: v_accvgpr_write_b32 a11, s19
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; AGPR-NEXT: v_accvgpr_write_b32 a12, s20
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; AGPR-NEXT: v_accvgpr_write_b32 a13, s21
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; AGPR-NEXT: v_accvgpr_write_b32 a14, s22
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; AGPR-NEXT: v_accvgpr_write_b32 a15, s23
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; AGPR-NEXT: v_mov_b32_e32 v16, s16
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; AGPR-NEXT: v_mov_b32_e32 v17, s17
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; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 a[16:31], v[8:11], v[12:15], a[0:15]
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; AGPR-NEXT: v_mov_b32_e32 v18, s18
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; AGPR-NEXT: v_mov_b32_e32 v19, s19
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; AGPR-NEXT: v_mov_b32_e32 v8, s20
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; AGPR-NEXT: v_mov_b32_e32 v9, s21
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; AGPR-NEXT: v_mov_b32_e32 v10, s22
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; AGPR-NEXT: v_mov_b32_e32 v11, s23
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; AGPR-NEXT: v_mov_b64_e32 v[6:7], 0
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; AGPR-NEXT: s_nop 4
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; AGPR-NEXT: global_store_dwordx4 v[0:1], a[28:31], off sc0 sc1
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; AGPR-NEXT: s_waitcnt vmcnt(0)
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; AGPR-NEXT: global_store_dwordx4 v[2:3], a[24:27], off sc0 sc1
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; AGPR-NEXT: s_waitcnt vmcnt(0)
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; AGPR-NEXT: global_store_dwordx4 v[4:5], a[20:23], off sc0 sc1
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; AGPR-NEXT: s_waitcnt vmcnt(0)
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; AGPR-NEXT: global_store_dwordx4 v[6:7], a[16:19], off sc0 sc1
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; AGPR-NEXT: s_waitcnt vmcnt(0)
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; AGPR-NEXT: global_store_dwordx4 v[2:3], v[16:19], off sc0 sc1
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; AGPR-NEXT: s_waitcnt vmcnt(0)
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; AGPR-NEXT: global_store_dwordx4 v[0:1], v[8:11], off sc0 sc1
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; AGPR-NEXT: s_waitcnt vmcnt(0)
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; AGPR-NEXT: v_mov_b32_e32 v0, s8
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; AGPR-NEXT: v_mov_b32_e32 v1, s9
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; AGPR-NEXT: v_mov_b32_e32 v2, s10
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; AGPR-NEXT: v_mov_b32_e32 v3, s11
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; AGPR-NEXT: global_store_dwordx4 v[6:7], v[0:3], off sc0 sc1
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; AGPR-NEXT: s_waitcnt vmcnt(0)
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; AGPR-NEXT: s_nop 0
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; AGPR-NEXT: v_mov_b32_e32 v0, s12
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; AGPR-NEXT: v_mov_b32_e32 v1, s13
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; AGPR-NEXT: v_mov_b32_e32 v2, s14
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; AGPR-NEXT: v_mov_b32_e32 v3, s15
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; AGPR-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1
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; AGPR-NEXT: s_waitcnt vmcnt(0)
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; AGPR-NEXT: s_endpgm
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;
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; VGPR-LABEL: test_mfma_f32_32x32x16_bf16:
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; VGPR: ; %bb.0:
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; VGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
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; VGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
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; VGPR-NEXT: v_mov_b64_e32 v[32:33], 48
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; VGPR-NEXT: v_mov_b64_e32 v[34:35], 32
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; VGPR-NEXT: v_mov_b64_e32 v[36:37], 16
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; VGPR-NEXT: s_waitcnt lgkmcnt(0)
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; VGPR-NEXT: v_mov_b64_e32 v[42:43], s[26:27]
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; VGPR-NEXT: v_mov_b64_e32 v[40:41], s[24:25]
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; VGPR-NEXT: v_mov_b64_e32 v[46:47], s[30:31]
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; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
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; VGPR-NEXT: v_mov_b64_e32 v[44:45], s[28:29]
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; VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
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; VGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
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; VGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
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; VGPR-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
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; VGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
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; VGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
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; VGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
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; VGPR-NEXT: v_mov_b32_e32 v48, s16
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; VGPR-NEXT: v_mov_b32_e32 v49, s17
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; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[16:31], v[40:43], v[44:47], v[0:15]
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; VGPR-NEXT: v_mov_b32_e32 v50, s18
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; VGPR-NEXT: v_mov_b32_e32 v51, s19
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; VGPR-NEXT: v_mov_b64_e32 v[38:39], 0
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; VGPR-NEXT: s_nop 8
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; VGPR-NEXT: global_store_dwordx4 v[32:33], v[28:31], off sc0 sc1
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; VGPR-NEXT: s_waitcnt vmcnt(0)
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; VGPR-NEXT: global_store_dwordx4 v[34:35], v[24:27], off sc0 sc1
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; VGPR-NEXT: s_waitcnt vmcnt(0)
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; VGPR-NEXT: global_store_dwordx4 v[36:37], v[20:23], off sc0 sc1
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; VGPR-NEXT: s_waitcnt vmcnt(0)
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; VGPR-NEXT: global_store_dwordx4 v[38:39], v[16:19], off sc0 sc1
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; VGPR-NEXT: s_waitcnt vmcnt(0)
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; VGPR-NEXT: v_mov_b32_e32 v0, s20
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; VGPR-NEXT: v_mov_b32_e32 v1, s21
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; VGPR-NEXT: v_mov_b32_e32 v2, s22
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; VGPR-NEXT: v_mov_b32_e32 v3, s23
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; VGPR-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
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; VGPR-NEXT: s_waitcnt vmcnt(0)
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; VGPR-NEXT: global_store_dwordx4 v[32:33], v[0:3], off sc0 sc1
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; VGPR-NEXT: s_waitcnt vmcnt(0)
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; VGPR-NEXT: s_nop 0
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; VGPR-NEXT: v_mov_b32_e32 v0, s8
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; VGPR-NEXT: v_mov_b32_e32 v1, s9
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; VGPR-NEXT: v_mov_b32_e32 v2, s10
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; VGPR-NEXT: v_mov_b32_e32 v3, s11
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; VGPR-NEXT: global_store_dwordx4 v[38:39], v[0:3], off sc0 sc1
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; VGPR-NEXT: s_waitcnt vmcnt(0)
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; VGPR-NEXT: s_nop 0
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; VGPR-NEXT: v_mov_b32_e32 v0, s12
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; VGPR-NEXT: v_mov_b32_e32 v1, s13
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; VGPR-NEXT: v_mov_b32_e32 v2, s14
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; VGPR-NEXT: v_mov_b32_e32 v3, s15
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; VGPR-NEXT: global_store_dwordx4 v[36:37], v[0:3], off sc0 sc1
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; VGPR-NEXT: s_waitcnt vmcnt(0)
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; VGPR-NEXT: s_endpgm
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%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 0, i32 0, i32 0)
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store volatile <16 x float> %result, ptr addrspace(1) null
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store volatile <16 x float> %arg2, ptr addrspace(1) null
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ret void
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}
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define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__flags(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2) #1 {
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; GCN-LABEL: test_mfma_f32_32x32x16_bf16__flags:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
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; GCN-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
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; GCN-NEXT: v_mov_b64_e32 v[0:1], 48
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; GCN-NEXT: v_mov_b64_e32 v[2:3], 32
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; GCN-NEXT: v_mov_b64_e32 v[4:5], 16
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b64_e32 v[8:9], s[24:25]
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; GCN-NEXT: v_mov_b64_e32 v[10:11], s[26:27]
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; GCN-NEXT: v_mov_b64_e32 v[12:13], s[28:29]
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; GCN-NEXT: v_accvgpr_write_b32 a0, s8
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; GCN-NEXT: v_mov_b64_e32 v[14:15], s[30:31]
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; GCN-NEXT: v_accvgpr_write_b32 a1, s9
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; GCN-NEXT: v_accvgpr_write_b32 a2, s10
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; GCN-NEXT: v_accvgpr_write_b32 a3, s11
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; GCN-NEXT: v_accvgpr_write_b32 a4, s12
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; GCN-NEXT: v_accvgpr_write_b32 a5, s13
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; GCN-NEXT: v_accvgpr_write_b32 a6, s14
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; GCN-NEXT: v_accvgpr_write_b32 a7, s15
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; GCN-NEXT: v_accvgpr_write_b32 a8, s16
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; GCN-NEXT: v_accvgpr_write_b32 a9, s17
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; GCN-NEXT: v_accvgpr_write_b32 a10, s18
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; GCN-NEXT: v_accvgpr_write_b32 a11, s19
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; GCN-NEXT: v_accvgpr_write_b32 a12, s20
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; GCN-NEXT: v_accvgpr_write_b32 a13, s21
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; GCN-NEXT: v_accvgpr_write_b32 a14, s22
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; GCN-NEXT: v_accvgpr_write_b32 a15, s23
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; GCN-NEXT: v_mov_b32_e32 v16, s16
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; GCN-NEXT: v_mov_b32_e32 v17, s17
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; GCN-NEXT: v_mfma_f32_32x32x16_bf16 a[16:31], v[8:11], v[12:15], a[0:15] cbsz:2 abid:3 blgp:1
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; GCN-NEXT: v_mov_b32_e32 v18, s18
|
|
; GCN-NEXT: v_mov_b32_e32 v19, s19
|
|
; GCN-NEXT: v_mov_b32_e32 v8, s20
|
|
; GCN-NEXT: v_mov_b32_e32 v9, s21
|
|
; GCN-NEXT: v_mov_b32_e32 v10, s22
|
|
; GCN-NEXT: v_mov_b32_e32 v11, s23
|
|
; GCN-NEXT: v_mov_b64_e32 v[6:7], 0
|
|
; GCN-NEXT: s_nop 4
|
|
; GCN-NEXT: global_store_dwordx4 v[0:1], a[28:31], off sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v[2:3], a[24:27], off sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v[4:5], a[20:23], off sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v[6:7], a[16:19], off sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v[2:3], v[16:19], off sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v[0:1], v[8:11], off sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: v_mov_b32_e32 v0, s8
|
|
; GCN-NEXT: v_mov_b32_e32 v1, s9
|
|
; GCN-NEXT: v_mov_b32_e32 v2, s10
|
|
; GCN-NEXT: v_mov_b32_e32 v3, s11
|
|
; GCN-NEXT: global_store_dwordx4 v[6:7], v[0:3], off sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: s_nop 0
|
|
; GCN-NEXT: v_mov_b32_e32 v0, s12
|
|
; GCN-NEXT: v_mov_b32_e32 v1, s13
|
|
; GCN-NEXT: v_mov_b32_e32 v2, s14
|
|
; GCN-NEXT: v_mov_b32_e32 v3, s15
|
|
; GCN-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__flags:
|
|
; AGPR: ; %bb.0:
|
|
; AGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; AGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; AGPR-NEXT: v_mov_b64_e32 v[0:1], 48
|
|
; AGPR-NEXT: v_mov_b64_e32 v[2:3], 32
|
|
; AGPR-NEXT: v_mov_b64_e32 v[4:5], 16
|
|
; AGPR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; AGPR-NEXT: v_mov_b64_e32 v[8:9], s[24:25]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[10:11], s[26:27]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[12:13], s[28:29]
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a0, s8
|
|
; AGPR-NEXT: v_mov_b64_e32 v[14:15], s[30:31]
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a1, s9
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a2, s10
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a3, s11
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a4, s12
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a5, s13
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a6, s14
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a7, s15
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a8, s16
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a9, s17
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a10, s18
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a11, s19
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a12, s20
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a13, s21
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a14, s22
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a15, s23
|
|
; AGPR-NEXT: v_mov_b32_e32 v16, s16
|
|
; AGPR-NEXT: v_mov_b32_e32 v17, s17
|
|
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 a[16:31], v[8:11], v[12:15], a[0:15] cbsz:2 abid:3 blgp:1
|
|
; AGPR-NEXT: v_mov_b32_e32 v18, s18
|
|
; AGPR-NEXT: v_mov_b32_e32 v19, s19
|
|
; AGPR-NEXT: v_mov_b32_e32 v8, s20
|
|
; AGPR-NEXT: v_mov_b32_e32 v9, s21
|
|
; AGPR-NEXT: v_mov_b32_e32 v10, s22
|
|
; AGPR-NEXT: v_mov_b32_e32 v11, s23
|
|
; AGPR-NEXT: v_mov_b64_e32 v[6:7], 0
|
|
; AGPR-NEXT: s_nop 4
|
|
; AGPR-NEXT: global_store_dwordx4 v[0:1], a[28:31], off sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v[2:3], a[24:27], off sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v[4:5], a[20:23], off sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v[6:7], a[16:19], off sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v[2:3], v[16:19], off sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v[0:1], v[8:11], off sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: v_mov_b32_e32 v0, s8
|
|
; AGPR-NEXT: v_mov_b32_e32 v1, s9
|
|
; AGPR-NEXT: v_mov_b32_e32 v2, s10
|
|
; AGPR-NEXT: v_mov_b32_e32 v3, s11
|
|
; AGPR-NEXT: global_store_dwordx4 v[6:7], v[0:3], off sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: s_nop 0
|
|
; AGPR-NEXT: v_mov_b32_e32 v0, s12
|
|
; AGPR-NEXT: v_mov_b32_e32 v1, s13
|
|
; AGPR-NEXT: v_mov_b32_e32 v2, s14
|
|
; AGPR-NEXT: v_mov_b32_e32 v3, s15
|
|
; AGPR-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: s_endpgm
|
|
;
|
|
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__flags:
|
|
; VGPR: ; %bb.0:
|
|
; VGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; VGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; VGPR-NEXT: v_mov_b64_e32 v[32:33], 48
|
|
; VGPR-NEXT: v_mov_b64_e32 v[34:35], 32
|
|
; VGPR-NEXT: v_mov_b64_e32 v[36:37], 16
|
|
; VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VGPR-NEXT: v_mov_b64_e32 v[42:43], s[26:27]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[40:41], s[24:25]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[46:47], s[30:31]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[44:45], s[28:29]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
|
; VGPR-NEXT: v_mov_b32_e32 v48, s16
|
|
; VGPR-NEXT: v_mov_b32_e32 v49, s17
|
|
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[16:31], v[40:43], v[44:47], v[0:15] cbsz:2 abid:3 blgp:1
|
|
; VGPR-NEXT: v_mov_b32_e32 v50, s18
|
|
; VGPR-NEXT: v_mov_b32_e32 v51, s19
|
|
; VGPR-NEXT: v_mov_b64_e32 v[38:39], 0
|
|
; VGPR-NEXT: s_nop 8
|
|
; VGPR-NEXT: global_store_dwordx4 v[32:33], v[28:31], off sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: global_store_dwordx4 v[34:35], v[24:27], off sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: global_store_dwordx4 v[36:37], v[20:23], off sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: global_store_dwordx4 v[38:39], v[16:19], off sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: v_mov_b32_e32 v0, s20
|
|
; VGPR-NEXT: v_mov_b32_e32 v1, s21
|
|
; VGPR-NEXT: v_mov_b32_e32 v2, s22
|
|
; VGPR-NEXT: v_mov_b32_e32 v3, s23
|
|
; VGPR-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: global_store_dwordx4 v[32:33], v[0:3], off sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: s_nop 0
|
|
; VGPR-NEXT: v_mov_b32_e32 v0, s8
|
|
; VGPR-NEXT: v_mov_b32_e32 v1, s9
|
|
; VGPR-NEXT: v_mov_b32_e32 v2, s10
|
|
; VGPR-NEXT: v_mov_b32_e32 v3, s11
|
|
; VGPR-NEXT: global_store_dwordx4 v[38:39], v[0:3], off sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: s_nop 0
|
|
; VGPR-NEXT: v_mov_b32_e32 v0, s12
|
|
; VGPR-NEXT: v_mov_b32_e32 v1, s13
|
|
; VGPR-NEXT: v_mov_b32_e32 v2, s14
|
|
; VGPR-NEXT: v_mov_b32_e32 v3, s15
|
|
; VGPR-NEXT: global_store_dwordx4 v[36:37], v[0:3], off sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: s_endpgm
|
|
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 2, i32 3, i32 1)
|
|
store volatile <16 x float> %result, ptr addrspace(1) null
|
|
store volatile <16 x float> %arg2, ptr addrspace(1) null
|
|
ret void
|
|
}
|
|
|
|
define <16 x float> @test_mfma_f32_32x32x16_bf16__mac(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2) {
|
|
; GCN-LABEL: test_mfma_f32_32x32x16_bf16__mac:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_accvgpr_write_b32 a0, v8
|
|
; GCN-NEXT: v_accvgpr_write_b32 a1, v9
|
|
; GCN-NEXT: v_accvgpr_write_b32 a2, v10
|
|
; GCN-NEXT: v_accvgpr_write_b32 a3, v11
|
|
; GCN-NEXT: v_accvgpr_write_b32 a4, v12
|
|
; GCN-NEXT: v_accvgpr_write_b32 a5, v13
|
|
; GCN-NEXT: v_accvgpr_write_b32 a6, v14
|
|
; GCN-NEXT: v_accvgpr_write_b32 a7, v15
|
|
; GCN-NEXT: v_accvgpr_write_b32 a8, v16
|
|
; GCN-NEXT: v_accvgpr_write_b32 a9, v17
|
|
; GCN-NEXT: v_accvgpr_write_b32 a10, v18
|
|
; GCN-NEXT: v_accvgpr_write_b32 a11, v19
|
|
; GCN-NEXT: v_accvgpr_write_b32 a12, v20
|
|
; GCN-NEXT: v_accvgpr_write_b32 a13, v21
|
|
; GCN-NEXT: v_accvgpr_write_b32 a14, v22
|
|
; GCN-NEXT: v_accvgpr_write_b32 a15, v23
|
|
; GCN-NEXT: s_nop 1
|
|
; GCN-NEXT: v_mfma_f32_32x32x16_bf16 a[0:15], v[0:3], v[4:7], a[0:15]
|
|
; GCN-NEXT: s_nop 11
|
|
; GCN-NEXT: v_accvgpr_read_b32 v0, a0
|
|
; GCN-NEXT: v_accvgpr_read_b32 v1, a1
|
|
; GCN-NEXT: v_accvgpr_read_b32 v2, a2
|
|
; GCN-NEXT: v_accvgpr_read_b32 v3, a3
|
|
; GCN-NEXT: v_accvgpr_read_b32 v4, a4
|
|
; GCN-NEXT: v_accvgpr_read_b32 v5, a5
|
|
; GCN-NEXT: v_accvgpr_read_b32 v6, a6
|
|
; GCN-NEXT: v_accvgpr_read_b32 v7, a7
|
|
; GCN-NEXT: v_accvgpr_read_b32 v8, a8
|
|
; GCN-NEXT: v_accvgpr_read_b32 v9, a9
|
|
; GCN-NEXT: v_accvgpr_read_b32 v10, a10
|
|
; GCN-NEXT: v_accvgpr_read_b32 v11, a11
|
|
; GCN-NEXT: v_accvgpr_read_b32 v12, a12
|
|
; GCN-NEXT: v_accvgpr_read_b32 v13, a13
|
|
; GCN-NEXT: v_accvgpr_read_b32 v14, a14
|
|
; GCN-NEXT: v_accvgpr_read_b32 v15, a15
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__mac:
|
|
; AGPR: ; %bb.0:
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a0, v8
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a1, v9
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a2, v10
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a3, v11
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a4, v12
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a5, v13
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a6, v14
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a7, v15
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a8, v16
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a9, v17
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a10, v18
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a11, v19
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a12, v20
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a13, v21
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a14, v22
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a15, v23
|
|
; AGPR-NEXT: s_nop 1
|
|
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 a[0:15], v[0:3], v[4:7], a[0:15]
|
|
; AGPR-NEXT: s_nop 11
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v0, a0
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v1, a1
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v2, a2
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v3, a3
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v4, a4
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v5, a5
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v6, a6
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v7, a7
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v8, a8
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v9, a9
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v10, a10
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v11, a11
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v12, a12
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v13, a13
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v14, a14
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v15, a15
|
|
; AGPR-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__mac:
|
|
; VGPR: ; %bb.0:
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[8:23], v[0:3], v[4:7], v[8:23]
|
|
; VGPR-NEXT: s_nop 11
|
|
; VGPR-NEXT: v_mov_b32_e32 v0, v8
|
|
; VGPR-NEXT: v_mov_b32_e32 v1, v9
|
|
; VGPR-NEXT: v_mov_b32_e32 v2, v10
|
|
; VGPR-NEXT: v_mov_b32_e32 v3, v11
|
|
; VGPR-NEXT: v_mov_b32_e32 v4, v12
|
|
; VGPR-NEXT: v_mov_b32_e32 v5, v13
|
|
; VGPR-NEXT: v_mov_b32_e32 v6, v14
|
|
; VGPR-NEXT: v_mov_b32_e32 v7, v15
|
|
; VGPR-NEXT: v_mov_b32_e32 v8, v16
|
|
; VGPR-NEXT: v_mov_b32_e32 v9, v17
|
|
; VGPR-NEXT: v_mov_b32_e32 v10, v18
|
|
; VGPR-NEXT: v_mov_b32_e32 v11, v19
|
|
; VGPR-NEXT: v_mov_b32_e32 v12, v20
|
|
; VGPR-NEXT: v_mov_b32_e32 v13, v21
|
|
; VGPR-NEXT: v_mov_b32_e32 v14, v22
|
|
; VGPR-NEXT: v_mov_b32_e32 v15, v23
|
|
; VGPR-NEXT: s_setpc_b64 s[30:31]
|
|
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 0, i32 0, i32 0)
|
|
ret <16 x float> %result
|
|
}
|
|
|
|
define <16 x float> @test_mfma_f32_32x32x16_bf16__mac__flags(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2) {
|
|
; GCN-LABEL: test_mfma_f32_32x32x16_bf16__mac__flags:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_accvgpr_write_b32 a0, v8
|
|
; GCN-NEXT: v_accvgpr_write_b32 a1, v9
|
|
; GCN-NEXT: v_accvgpr_write_b32 a2, v10
|
|
; GCN-NEXT: v_accvgpr_write_b32 a3, v11
|
|
; GCN-NEXT: v_accvgpr_write_b32 a4, v12
|
|
; GCN-NEXT: v_accvgpr_write_b32 a5, v13
|
|
; GCN-NEXT: v_accvgpr_write_b32 a6, v14
|
|
; GCN-NEXT: v_accvgpr_write_b32 a7, v15
|
|
; GCN-NEXT: v_accvgpr_write_b32 a8, v16
|
|
; GCN-NEXT: v_accvgpr_write_b32 a9, v17
|
|
; GCN-NEXT: v_accvgpr_write_b32 a10, v18
|
|
; GCN-NEXT: v_accvgpr_write_b32 a11, v19
|
|
; GCN-NEXT: v_accvgpr_write_b32 a12, v20
|
|
; GCN-NEXT: v_accvgpr_write_b32 a13, v21
|
|
; GCN-NEXT: v_accvgpr_write_b32 a14, v22
|
|
; GCN-NEXT: v_accvgpr_write_b32 a15, v23
|
|
; GCN-NEXT: s_nop 1
|
|
; GCN-NEXT: v_mfma_f32_32x32x16_bf16 a[0:15], v[0:3], v[4:7], a[0:15] cbsz:1 abid:1 blgp:1
|
|
; GCN-NEXT: s_nop 11
|
|
; GCN-NEXT: v_accvgpr_read_b32 v0, a0
|
|
; GCN-NEXT: v_accvgpr_read_b32 v1, a1
|
|
; GCN-NEXT: v_accvgpr_read_b32 v2, a2
|
|
; GCN-NEXT: v_accvgpr_read_b32 v3, a3
|
|
; GCN-NEXT: v_accvgpr_read_b32 v4, a4
|
|
; GCN-NEXT: v_accvgpr_read_b32 v5, a5
|
|
; GCN-NEXT: v_accvgpr_read_b32 v6, a6
|
|
; GCN-NEXT: v_accvgpr_read_b32 v7, a7
|
|
; GCN-NEXT: v_accvgpr_read_b32 v8, a8
|
|
; GCN-NEXT: v_accvgpr_read_b32 v9, a9
|
|
; GCN-NEXT: v_accvgpr_read_b32 v10, a10
|
|
; GCN-NEXT: v_accvgpr_read_b32 v11, a11
|
|
; GCN-NEXT: v_accvgpr_read_b32 v12, a12
|
|
; GCN-NEXT: v_accvgpr_read_b32 v13, a13
|
|
; GCN-NEXT: v_accvgpr_read_b32 v14, a14
|
|
; GCN-NEXT: v_accvgpr_read_b32 v15, a15
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__mac__flags:
|
|
; AGPR: ; %bb.0:
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a0, v8
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a1, v9
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a2, v10
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a3, v11
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a4, v12
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a5, v13
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a6, v14
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a7, v15
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a8, v16
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a9, v17
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a10, v18
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a11, v19
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a12, v20
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a13, v21
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a14, v22
|
|
; AGPR-NEXT: v_accvgpr_write_b32 a15, v23
|
|
; AGPR-NEXT: s_nop 1
|
|
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 a[0:15], v[0:3], v[4:7], a[0:15] cbsz:1 abid:1 blgp:1
|
|
; AGPR-NEXT: s_nop 11
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v0, a0
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v1, a1
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v2, a2
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v3, a3
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v4, a4
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v5, a5
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v6, a6
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v7, a7
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v8, a8
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v9, a9
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v10, a10
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v11, a11
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v12, a12
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v13, a13
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v14, a14
|
|
; AGPR-NEXT: v_accvgpr_read_b32 v15, a15
|
|
; AGPR-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__mac__flags:
|
|
; VGPR: ; %bb.0:
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[8:23], v[0:3], v[4:7], v[8:23] cbsz:1 abid:1 blgp:1
|
|
; VGPR-NEXT: s_nop 11
|
|
; VGPR-NEXT: v_mov_b32_e32 v0, v8
|
|
; VGPR-NEXT: v_mov_b32_e32 v1, v9
|
|
; VGPR-NEXT: v_mov_b32_e32 v2, v10
|
|
; VGPR-NEXT: v_mov_b32_e32 v3, v11
|
|
; VGPR-NEXT: v_mov_b32_e32 v4, v12
|
|
; VGPR-NEXT: v_mov_b32_e32 v5, v13
|
|
; VGPR-NEXT: v_mov_b32_e32 v6, v14
|
|
; VGPR-NEXT: v_mov_b32_e32 v7, v15
|
|
; VGPR-NEXT: v_mov_b32_e32 v8, v16
|
|
; VGPR-NEXT: v_mov_b32_e32 v9, v17
|
|
; VGPR-NEXT: v_mov_b32_e32 v10, v18
|
|
; VGPR-NEXT: v_mov_b32_e32 v11, v19
|
|
; VGPR-NEXT: v_mov_b32_e32 v12, v20
|
|
; VGPR-NEXT: v_mov_b32_e32 v13, v21
|
|
; VGPR-NEXT: v_mov_b32_e32 v14, v22
|
|
; VGPR-NEXT: v_mov_b32_e32 v15, v23
|
|
; VGPR-NEXT: s_setpc_b64 s[30:31]
|
|
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 1, i32 1, i32 1)
|
|
ret <16 x float> %result
|
|
}
|
|
|
|
define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, ptr addrspace(1) %out) #0 {
|
|
; GCN-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; GCN-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
|
; GCN-NEXT: v_mov_b32_e32 v36, 0
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
|
|
; GCN-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
|
|
; GCN-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
|
|
; GCN-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
|
|
; GCN-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
|
|
; GCN-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
|
|
; GCN-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
|
|
; GCN-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
|
|
; GCN-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
|
|
; GCN-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
|
|
; GCN-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
|
|
; GCN-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
|
|
; GCN-NEXT: v_mov_b32_e32 v32, s20
|
|
; GCN-NEXT: v_mov_b32_e32 v33, s21
|
|
; GCN-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[38:41], v[42:45], v[16:31]
|
|
; GCN-NEXT: v_mov_b32_e32 v34, s22
|
|
; GCN-NEXT: v_mov_b32_e32 v35, s23
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[32:35], s[0:1] offset:48 sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: s_nop 2
|
|
; GCN-NEXT: v_mov_b32_e32 v16, s16
|
|
; GCN-NEXT: v_mov_b32_e32 v17, s17
|
|
; GCN-NEXT: v_mov_b32_e32 v18, s18
|
|
; GCN-NEXT: v_mov_b32_e32 v19, s19
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:32 sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: s_nop 0
|
|
; GCN-NEXT: v_mov_b32_e32 v16, s12
|
|
; GCN-NEXT: v_mov_b32_e32 v17, s13
|
|
; GCN-NEXT: v_mov_b32_e32 v18, s14
|
|
; GCN-NEXT: v_mov_b32_e32 v19, s15
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:16 sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: s_nop 0
|
|
; GCN-NEXT: v_mov_b32_e32 v16, s8
|
|
; GCN-NEXT: v_mov_b32_e32 v17, s9
|
|
; GCN-NEXT: v_mov_b32_e32 v18, s10
|
|
; GCN-NEXT: v_mov_b32_e32 v19, s11
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[8:11], s[0:1] offset:32 sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[12:15], s[0:1] offset:48 sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[0:3], s[0:1] sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:16 sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd:
|
|
; AGPR: ; %bb.0:
|
|
; AGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; AGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; AGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
|
; AGPR-NEXT: v_mov_b32_e32 v36, 0
|
|
; AGPR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; AGPR-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
|
|
; AGPR-NEXT: v_mov_b32_e32 v32, s20
|
|
; AGPR-NEXT: v_mov_b32_e32 v33, s21
|
|
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[38:41], v[42:45], v[16:31]
|
|
; AGPR-NEXT: v_mov_b32_e32 v34, s22
|
|
; AGPR-NEXT: v_mov_b32_e32 v35, s23
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[32:35], s[0:1] offset:48 sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: s_nop 2
|
|
; AGPR-NEXT: v_mov_b32_e32 v16, s16
|
|
; AGPR-NEXT: v_mov_b32_e32 v17, s17
|
|
; AGPR-NEXT: v_mov_b32_e32 v18, s18
|
|
; AGPR-NEXT: v_mov_b32_e32 v19, s19
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:32 sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: s_nop 0
|
|
; AGPR-NEXT: v_mov_b32_e32 v16, s12
|
|
; AGPR-NEXT: v_mov_b32_e32 v17, s13
|
|
; AGPR-NEXT: v_mov_b32_e32 v18, s14
|
|
; AGPR-NEXT: v_mov_b32_e32 v19, s15
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:16 sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: s_nop 0
|
|
; AGPR-NEXT: v_mov_b32_e32 v16, s8
|
|
; AGPR-NEXT: v_mov_b32_e32 v17, s9
|
|
; AGPR-NEXT: v_mov_b32_e32 v18, s10
|
|
; AGPR-NEXT: v_mov_b32_e32 v19, s11
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[8:11], s[0:1] offset:32 sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[12:15], s[0:1] offset:48 sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[0:3], s[0:1] sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:16 sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: s_endpgm
|
|
;
|
|
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd:
|
|
; VGPR: ; %bb.0:
|
|
; VGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; VGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; VGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
|
; VGPR-NEXT: v_mov_b32_e32 v36, 0
|
|
; VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VGPR-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
|
|
; VGPR-NEXT: v_mov_b32_e32 v32, s20
|
|
; VGPR-NEXT: v_mov_b32_e32 v33, s21
|
|
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[38:41], v[42:45], v[16:31]
|
|
; VGPR-NEXT: v_mov_b32_e32 v34, s22
|
|
; VGPR-NEXT: v_mov_b32_e32 v35, s23
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[32:35], s[0:1] offset:48 sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: s_nop 2
|
|
; VGPR-NEXT: v_mov_b32_e32 v16, s16
|
|
; VGPR-NEXT: v_mov_b32_e32 v17, s17
|
|
; VGPR-NEXT: v_mov_b32_e32 v18, s18
|
|
; VGPR-NEXT: v_mov_b32_e32 v19, s19
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:32 sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: s_nop 0
|
|
; VGPR-NEXT: v_mov_b32_e32 v16, s12
|
|
; VGPR-NEXT: v_mov_b32_e32 v17, s13
|
|
; VGPR-NEXT: v_mov_b32_e32 v18, s14
|
|
; VGPR-NEXT: v_mov_b32_e32 v19, s15
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:16 sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: s_nop 0
|
|
; VGPR-NEXT: v_mov_b32_e32 v16, s8
|
|
; VGPR-NEXT: v_mov_b32_e32 v17, s9
|
|
; VGPR-NEXT: v_mov_b32_e32 v18, s10
|
|
; VGPR-NEXT: v_mov_b32_e32 v19, s11
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[8:11], s[0:1] offset:32 sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[12:15], s[0:1] offset:48 sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[0:3], s[0:1] sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:16 sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: s_endpgm
|
|
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 0, i32 0, i32 0)
|
|
store volatile <16 x float> %arg2, ptr addrspace(1) %out
|
|
store volatile <16 x float> %result, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd__flags(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, ptr addrspace(1) %out) #0 {
|
|
; GCN-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd__flags:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; GCN-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
|
; GCN-NEXT: v_mov_b32_e32 v36, 0
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
|
|
; GCN-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
|
|
; GCN-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
|
|
; GCN-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
|
|
; GCN-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
|
|
; GCN-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
|
|
; GCN-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
|
|
; GCN-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
|
|
; GCN-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
|
|
; GCN-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
|
|
; GCN-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
|
|
; GCN-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
|
|
; GCN-NEXT: v_mov_b32_e32 v32, s20
|
|
; GCN-NEXT: v_mov_b32_e32 v33, s21
|
|
; GCN-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[38:41], v[42:45], v[16:31] cbsz:1 abid:2 blgp:3
|
|
; GCN-NEXT: v_mov_b32_e32 v34, s22
|
|
; GCN-NEXT: v_mov_b32_e32 v35, s23
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[32:35], s[0:1] offset:48 sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: s_nop 2
|
|
; GCN-NEXT: v_mov_b32_e32 v16, s16
|
|
; GCN-NEXT: v_mov_b32_e32 v17, s17
|
|
; GCN-NEXT: v_mov_b32_e32 v18, s18
|
|
; GCN-NEXT: v_mov_b32_e32 v19, s19
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:32 sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: s_nop 0
|
|
; GCN-NEXT: v_mov_b32_e32 v16, s12
|
|
; GCN-NEXT: v_mov_b32_e32 v17, s13
|
|
; GCN-NEXT: v_mov_b32_e32 v18, s14
|
|
; GCN-NEXT: v_mov_b32_e32 v19, s15
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:16 sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: s_nop 0
|
|
; GCN-NEXT: v_mov_b32_e32 v16, s8
|
|
; GCN-NEXT: v_mov_b32_e32 v17, s9
|
|
; GCN-NEXT: v_mov_b32_e32 v18, s10
|
|
; GCN-NEXT: v_mov_b32_e32 v19, s11
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[8:11], s[0:1] offset:32 sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[12:15], s[0:1] offset:48 sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[0:3], s[0:1] sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:16 sc0 sc1
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd__flags:
|
|
; AGPR: ; %bb.0:
|
|
; AGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; AGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; AGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
|
; AGPR-NEXT: v_mov_b32_e32 v36, 0
|
|
; AGPR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; AGPR-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
|
|
; AGPR-NEXT: v_mov_b32_e32 v32, s20
|
|
; AGPR-NEXT: v_mov_b32_e32 v33, s21
|
|
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[38:41], v[42:45], v[16:31] cbsz:1 abid:2 blgp:3
|
|
; AGPR-NEXT: v_mov_b32_e32 v34, s22
|
|
; AGPR-NEXT: v_mov_b32_e32 v35, s23
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[32:35], s[0:1] offset:48 sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: s_nop 2
|
|
; AGPR-NEXT: v_mov_b32_e32 v16, s16
|
|
; AGPR-NEXT: v_mov_b32_e32 v17, s17
|
|
; AGPR-NEXT: v_mov_b32_e32 v18, s18
|
|
; AGPR-NEXT: v_mov_b32_e32 v19, s19
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:32 sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: s_nop 0
|
|
; AGPR-NEXT: v_mov_b32_e32 v16, s12
|
|
; AGPR-NEXT: v_mov_b32_e32 v17, s13
|
|
; AGPR-NEXT: v_mov_b32_e32 v18, s14
|
|
; AGPR-NEXT: v_mov_b32_e32 v19, s15
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:16 sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: s_nop 0
|
|
; AGPR-NEXT: v_mov_b32_e32 v16, s8
|
|
; AGPR-NEXT: v_mov_b32_e32 v17, s9
|
|
; AGPR-NEXT: v_mov_b32_e32 v18, s10
|
|
; AGPR-NEXT: v_mov_b32_e32 v19, s11
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[8:11], s[0:1] offset:32 sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[12:15], s[0:1] offset:48 sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[0:3], s[0:1] sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:16 sc0 sc1
|
|
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; AGPR-NEXT: s_endpgm
|
|
;
|
|
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd__flags:
|
|
; VGPR: ; %bb.0:
|
|
; VGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; VGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; VGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
|
; VGPR-NEXT: v_mov_b32_e32 v36, 0
|
|
; VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VGPR-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
|
|
; VGPR-NEXT: v_mov_b32_e32 v32, s20
|
|
; VGPR-NEXT: v_mov_b32_e32 v33, s21
|
|
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[38:41], v[42:45], v[16:31] cbsz:1 abid:2 blgp:3
|
|
; VGPR-NEXT: v_mov_b32_e32 v34, s22
|
|
; VGPR-NEXT: v_mov_b32_e32 v35, s23
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[32:35], s[0:1] offset:48 sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: s_nop 2
|
|
; VGPR-NEXT: v_mov_b32_e32 v16, s16
|
|
; VGPR-NEXT: v_mov_b32_e32 v17, s17
|
|
; VGPR-NEXT: v_mov_b32_e32 v18, s18
|
|
; VGPR-NEXT: v_mov_b32_e32 v19, s19
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:32 sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: s_nop 0
|
|
; VGPR-NEXT: v_mov_b32_e32 v16, s12
|
|
; VGPR-NEXT: v_mov_b32_e32 v17, s13
|
|
; VGPR-NEXT: v_mov_b32_e32 v18, s14
|
|
; VGPR-NEXT: v_mov_b32_e32 v19, s15
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:16 sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: s_nop 0
|
|
; VGPR-NEXT: v_mov_b32_e32 v16, s8
|
|
; VGPR-NEXT: v_mov_b32_e32 v17, s9
|
|
; VGPR-NEXT: v_mov_b32_e32 v18, s10
|
|
; VGPR-NEXT: v_mov_b32_e32 v19, s11
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[8:11], s[0:1] offset:32 sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[12:15], s[0:1] offset:48 sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[0:3], s[0:1] sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:16 sc0 sc1
|
|
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
|
; VGPR-NEXT: s_endpgm
|
|
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 1, i32 2, i32 3)
|
|
store volatile <16 x float> %arg2, ptr addrspace(1) %out
|
|
store volatile <16 x float> %result, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd_mac(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, ptr addrspace(1) %out) #0 {
|
|
; GCN-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd_mac:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; GCN-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
|
|
; GCN-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
|
|
; GCN-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
|
|
; GCN-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
|
; GCN-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
|
|
; GCN-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
|
; GCN-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
|
; GCN-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
|
; GCN-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
|
; GCN-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
|
; GCN-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
|
; GCN-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
|
; GCN-NEXT: s_nop 1
|
|
; GCN-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[16:19], v[20:23], v[0:15]
|
|
; GCN-NEXT: v_mov_b32_e32 v16, 0
|
|
; GCN-NEXT: s_nop 10
|
|
; GCN-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1] offset:48
|
|
; GCN-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:32
|
|
; GCN-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
|
|
; GCN-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1]
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd_mac:
|
|
; AGPR: ; %bb.0:
|
|
; AGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; AGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; AGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
|
; AGPR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; AGPR-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
|
; AGPR-NEXT: s_nop 1
|
|
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[16:19], v[20:23], v[0:15]
|
|
; AGPR-NEXT: v_mov_b32_e32 v16, 0
|
|
; AGPR-NEXT: s_nop 10
|
|
; AGPR-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1] offset:48
|
|
; AGPR-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:32
|
|
; AGPR-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
|
|
; AGPR-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1]
|
|
; AGPR-NEXT: s_endpgm
|
|
;
|
|
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd_mac:
|
|
; VGPR: ; %bb.0:
|
|
; VGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; VGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; VGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
|
; VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VGPR-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
|
; VGPR-NEXT: s_nop 1
|
|
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[16:19], v[20:23], v[0:15]
|
|
; VGPR-NEXT: v_mov_b32_e32 v16, 0
|
|
; VGPR-NEXT: s_nop 10
|
|
; VGPR-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1] offset:48
|
|
; VGPR-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:32
|
|
; VGPR-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
|
|
; VGPR-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1]
|
|
; VGPR-NEXT: s_endpgm
|
|
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 0, i32 0, i32 0)
|
|
store <16 x float> %result, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd_mac_flags(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, ptr addrspace(1) %out) #0 {
|
|
; GCN-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd_mac_flags:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; GCN-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
|
|
; GCN-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
|
|
; GCN-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
|
|
; GCN-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
|
; GCN-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
|
|
; GCN-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
|
; GCN-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
|
; GCN-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
|
; GCN-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
|
; GCN-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
|
; GCN-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
|
; GCN-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
|
; GCN-NEXT: s_nop 1
|
|
; GCN-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[16:19], v[20:23], v[0:15] cbsz:3 abid:2 blgp:1
|
|
; GCN-NEXT: v_mov_b32_e32 v16, 0
|
|
; GCN-NEXT: s_nop 10
|
|
; GCN-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1] offset:48
|
|
; GCN-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:32
|
|
; GCN-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
|
|
; GCN-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1]
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd_mac_flags:
|
|
; AGPR: ; %bb.0:
|
|
; AGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; AGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; AGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
|
; AGPR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; AGPR-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
|
; AGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
|
; AGPR-NEXT: s_nop 1
|
|
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[16:19], v[20:23], v[0:15] cbsz:3 abid:2 blgp:1
|
|
; AGPR-NEXT: v_mov_b32_e32 v16, 0
|
|
; AGPR-NEXT: s_nop 10
|
|
; AGPR-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1] offset:48
|
|
; AGPR-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:32
|
|
; AGPR-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
|
|
; AGPR-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1]
|
|
; AGPR-NEXT: s_endpgm
|
|
;
|
|
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd_mac_flags:
|
|
; VGPR: ; %bb.0:
|
|
; VGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
|
; VGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
|
; VGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
|
; VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VGPR-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
|
; VGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
|
; VGPR-NEXT: s_nop 1
|
|
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[16:19], v[20:23], v[0:15] cbsz:3 abid:2 blgp:1
|
|
; VGPR-NEXT: v_mov_b32_e32 v16, 0
|
|
; VGPR-NEXT: s_nop 10
|
|
; VGPR-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1] offset:48
|
|
; VGPR-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:32
|
|
; VGPR-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
|
|
; VGPR-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1]
|
|
; VGPR-NEXT: s_endpgm
|
|
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 3, i32 2, i32 1)
|
|
store <16 x float> %result, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { "amdgpu-flat-work-group-size"="512,512" "amdgpu-agpr-alloc"="0,0" }
|
|
attributes #1 = { "amdgpu-flat-work-group-size"="1,64" }
|