derek.holloway
7502bf64a4
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45 lines
1.6 KiB
LLVM
45 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s
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; Check that the ds_load_b32 instruction is not sunk past the
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; fence-barrier-fence sequence.
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define amdgpu_kernel void @test_fence(ptr addrspace(1) %arg, i1 %arg1) {
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; CHECK-LABEL: test_fence:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: s_load_b32 s0, s[4:5], 0x2c
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; CHECK-NEXT: ds_load_b32 v1, v1
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; CHECK-NEXT: s_wait_kmcnt 0x0
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; CHECK-NEXT: s_bitcmp0_b32 s0, 0
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; CHECK-NEXT: s_wait_dscnt 0x0
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; CHECK-NEXT: s_barrier_signal -1
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; CHECK-NEXT: s_barrier_wait -1
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; CHECK-NEXT: global_inv scope:SCOPE_SE
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; CHECK-NEXT: s_cbranch_scc1 .LBB0_2
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; CHECK-NEXT: ; %bb.1: ; %bb2
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; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; CHECK-NEXT: s_wait_kmcnt 0x0
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; CHECK-NEXT: global_atomic_add_u32 v0, v1, s[0:1] scope:SCOPE_SYS
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; CHECK-NEXT: .LBB0_2: ; %bb8
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; CHECK-NEXT: s_endpgm
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bb:
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%i6 = load i32, ptr addrspace(3) null
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fence syncscope("workgroup") release
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tail call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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tail call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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fence syncscope("workgroup") acquire
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br i1 %arg1, label %bb2, label %bb8
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bb2:
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%i3 = tail call i32 @llvm.amdgcn.workitem.id.x()
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%i5 = getelementptr i32, ptr addrspace(1) %arg, i32 %i3
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%i7 = atomicrmw add ptr addrspace(1) %i5, i32 %i6 monotonic
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br label %bb8
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bb8:
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ret void
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}
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