derek.holloway
7502bf64a4
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188 lines
6.8 KiB
LLVM
188 lines
6.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GFX10-WGP %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1010 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX10-CU %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GFX11-WGP %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1100 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX11-CU %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX12-WGP %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1200 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX12-CU %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250 %s
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define amdgpu_kernel void @test_s_barrier() {
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; GFX10-WGP-LABEL: test_s_barrier:
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; GFX10-WGP: ; %bb.0: ; %entry
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; GFX10-WGP-NEXT: s_barrier
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; GFX10-WGP-NEXT: s_endpgm
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;
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; GFX10-CU-LABEL: test_s_barrier:
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; GFX10-CU: ; %bb.0: ; %entry
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; GFX10-CU-NEXT: s_barrier
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; GFX10-CU-NEXT: s_endpgm
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;
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; GFX11-WGP-LABEL: test_s_barrier:
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; GFX11-WGP: ; %bb.0: ; %entry
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; GFX11-WGP-NEXT: s_barrier
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; GFX11-WGP-NEXT: s_endpgm
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;
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; GFX11-CU-LABEL: test_s_barrier:
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; GFX11-CU: ; %bb.0: ; %entry
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; GFX11-CU-NEXT: s_barrier
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; GFX11-CU-NEXT: s_endpgm
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;
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; GFX12-WGP-LABEL: test_s_barrier:
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; GFX12-WGP: ; %bb.0: ; %entry
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; GFX12-WGP-NEXT: s_barrier_signal -1
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; GFX12-WGP-NEXT: s_barrier_wait -1
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; GFX12-WGP-NEXT: s_endpgm
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;
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; GFX12-CU-LABEL: test_s_barrier:
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; GFX12-CU: ; %bb.0: ; %entry
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; GFX12-CU-NEXT: s_barrier_signal -1
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; GFX12-CU-NEXT: s_barrier_wait -1
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; GFX12-CU-NEXT: s_endpgm
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;
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; GFX1250-LABEL: test_s_barrier:
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; GFX1250: ; %bb.0: ; %entry
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_barrier_signal -1
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; GFX1250-NEXT: s_barrier_wait -1
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; GFX1250-NEXT: s_endpgm
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entry:
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call void @llvm.amdgcn.s.barrier()
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ret void
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}
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define amdgpu_kernel void @test_s_barrier_workgroup_fence() {
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; GFX10-WGP-LABEL: test_s_barrier_workgroup_fence:
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; GFX10-WGP: ; %bb.0: ; %entry
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; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-WGP-NEXT: s_barrier
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; GFX10-WGP-NEXT: s_endpgm
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;
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; GFX10-CU-LABEL: test_s_barrier_workgroup_fence:
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; GFX10-CU: ; %bb.0: ; %entry
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; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-CU-NEXT: s_barrier
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; GFX10-CU-NEXT: s_endpgm
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;
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; GFX11-WGP-LABEL: test_s_barrier_workgroup_fence:
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; GFX11-WGP: ; %bb.0: ; %entry
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; GFX11-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX11-WGP-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-WGP-NEXT: s_barrier
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; GFX11-WGP-NEXT: s_endpgm
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;
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; GFX11-CU-LABEL: test_s_barrier_workgroup_fence:
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; GFX11-CU: ; %bb.0: ; %entry
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; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-CU-NEXT: s_barrier
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; GFX11-CU-NEXT: s_endpgm
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;
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; GFX12-WGP-LABEL: test_s_barrier_workgroup_fence:
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; GFX12-WGP: ; %bb.0: ; %entry
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; GFX12-WGP-NEXT: s_wait_bvhcnt 0x0
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; GFX12-WGP-NEXT: s_wait_samplecnt 0x0
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; GFX12-WGP-NEXT: s_wait_storecnt 0x0
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; GFX12-WGP-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-WGP-NEXT: s_barrier_signal -1
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; GFX12-WGP-NEXT: s_barrier_wait -1
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; GFX12-WGP-NEXT: s_endpgm
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;
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; GFX12-CU-LABEL: test_s_barrier_workgroup_fence:
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; GFX12-CU: ; %bb.0: ; %entry
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; GFX12-CU-NEXT: s_wait_bvhcnt 0x0
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; GFX12-CU-NEXT: s_wait_samplecnt 0x0
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; GFX12-CU-NEXT: s_wait_storecnt 0x0
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; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-CU-NEXT: s_barrier_signal -1
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; GFX12-CU-NEXT: s_barrier_wait -1
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; GFX12-CU-NEXT: s_endpgm
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;
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; GFX1250-LABEL: test_s_barrier_workgroup_fence:
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; GFX1250: ; %bb.0: ; %entry
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_wait_storecnt 0x0
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_barrier_signal -1
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; GFX1250-NEXT: s_barrier_wait -1
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; GFX1250-NEXT: s_endpgm
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entry:
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fence syncscope("workgroup") release
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call void @llvm.amdgcn.s.barrier()
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ret void
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}
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define amdgpu_kernel void @test_s_barrier_agent_fence() {
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; GFX10-WGP-LABEL: test_s_barrier_agent_fence:
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; GFX10-WGP: ; %bb.0: ; %entry
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; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-WGP-NEXT: s_barrier
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; GFX10-WGP-NEXT: s_endpgm
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;
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; GFX10-CU-LABEL: test_s_barrier_agent_fence:
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; GFX10-CU: ; %bb.0: ; %entry
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; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-CU-NEXT: s_barrier
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; GFX10-CU-NEXT: s_endpgm
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;
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; GFX11-WGP-LABEL: test_s_barrier_agent_fence:
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; GFX11-WGP: ; %bb.0: ; %entry
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; GFX11-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX11-WGP-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-WGP-NEXT: s_barrier
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; GFX11-WGP-NEXT: s_endpgm
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;
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; GFX11-CU-LABEL: test_s_barrier_agent_fence:
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; GFX11-CU: ; %bb.0: ; %entry
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; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-CU-NEXT: s_barrier
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; GFX11-CU-NEXT: s_endpgm
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;
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; GFX12-WGP-LABEL: test_s_barrier_agent_fence:
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; GFX12-WGP: ; %bb.0: ; %entry
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; GFX12-WGP-NEXT: s_wait_bvhcnt 0x0
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; GFX12-WGP-NEXT: s_wait_samplecnt 0x0
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; GFX12-WGP-NEXT: s_wait_storecnt 0x0
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; GFX12-WGP-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-WGP-NEXT: s_barrier_signal -1
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; GFX12-WGP-NEXT: s_barrier_wait -1
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; GFX12-WGP-NEXT: s_endpgm
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;
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; GFX12-CU-LABEL: test_s_barrier_agent_fence:
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; GFX12-CU: ; %bb.0: ; %entry
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; GFX12-CU-NEXT: s_wait_bvhcnt 0x0
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; GFX12-CU-NEXT: s_wait_samplecnt 0x0
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; GFX12-CU-NEXT: s_wait_storecnt 0x0
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; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-CU-NEXT: s_barrier_signal -1
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; GFX12-CU-NEXT: s_barrier_wait -1
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; GFX12-CU-NEXT: s_endpgm
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;
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; GFX1250-LABEL: test_s_barrier_agent_fence:
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; GFX1250: ; %bb.0: ; %entry
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_wait_loadcnt 0x0
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; GFX1250-NEXT: s_wait_storecnt 0x0
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; GFX1250-NEXT: global_wb scope:SCOPE_DEV
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; GFX1250-NEXT: s_wait_storecnt 0x0
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_barrier_signal -1
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; GFX1250-NEXT: s_barrier_wait -1
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; GFX1250-NEXT: s_endpgm
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entry:
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fence syncscope("agent") release
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call void @llvm.amdgcn.s.barrier()
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ret void
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}
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