derek.holloway
7502bf64a4
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192 lines
7.8 KiB
LLVM
192 lines
7.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s
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; Test that negative 64-bit values shifted by [32-63] bits have
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; a hi-result created by moving an all-ones constant.
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; FIXME: Range metadata is invalidated when i64 types are legalized to v2i32 types.
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; We could call performSraCombine before legalization, but other optimizations only work
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; with 64-bit sra.
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define i64 @scalar_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {
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; CHECK-LABEL: scalar_ashr_metadata:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dwordx2 v[4:5], v[0:1]
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dword v4, v[2:3]
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; CHECK-NEXT: ; kill: killed $vgpr0 killed $vgpr1
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; CHECK-NEXT: ; kill: killed $vgpr2 killed $vgpr3
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; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v5
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_ashrrev_i32_e32 v0, v4, v5
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%val = load i64, ptr %arg0.ptr, !range !0, !noundef !{}
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%shift.amt = load i64, ptr %arg1.ptr, !range !1, !noundef !{}
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%ashr = ashr i64 %val, %shift.amt
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ret i64 %ashr
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}
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define <2 x i64> @v2_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {
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; CHECK-LABEL: v2_ashr_metadata:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
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; CHECK-NEXT: flat_load_dwordx4 v[8:11], v[2:3]
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; CHECK-NEXT: v_mov_b32_e32 v1, -1
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; CHECK-NEXT: v_mov_b32_e32 v3, -1
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_ashrrev_i32_e32 v0, v8, v5
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; CHECK-NEXT: v_ashrrev_i32_e32 v2, v10, v7
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%val = load <2 x i64>, ptr %arg0.ptr, !range !2, !noundef !{}
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%shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !3, !noundef !{}
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%ashr = ashr <2 x i64> %val, %shift.amt
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ret <2 x i64> %ashr
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}
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define <3 x i64> @v3_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {
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; CHECK-LABEL: v3_ashr_metadata:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
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; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 20, v0
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; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dword v4, v[2:3] offset:16
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; CHECK-NEXT: flat_load_dwordx4 v[8:11], v[2:3]
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; CHECK-NEXT: v_mov_b32_e32 v3, -1
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; CHECK-NEXT: flat_load_dword v1, v[0:1]
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_ashrrev_i32_e32 v0, v8, v5
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; CHECK-NEXT: v_ashrrev_i32_e32 v2, v10, v7
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; CHECK-NEXT: v_ashrrev_i32_e32 v4, v4, v1
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; CHECK-NEXT: v_mov_b32_e32 v1, -1
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; CHECK-NEXT: v_mov_b32_e32 v5, -1
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%val = load <3 x i64>, ptr %arg0.ptr, !range !4, !noundef !{}
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%shift.amt = load <3 x i64>, ptr %arg1.ptr, !range !5, !noundef !{}
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%ashr = ashr <3 x i64> %val, %shift.amt
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ret <3 x i64> %ashr
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}
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define <4 x i64> @v4_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {
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; CHECK-LABEL: v4_ashr_metadata:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[2:3]
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dwordx4 v[7:10], v[0:1]
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; CHECK-NEXT: flat_load_dwordx4 v[11:14], v[0:1] offset:16
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; CHECK-NEXT: flat_load_dwordx4 v[15:18], v[2:3] offset:16
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; CHECK-NEXT: v_mov_b32_e32 v1, -1
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; CHECK-NEXT: v_mov_b32_e32 v3, -1
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; CHECK-NEXT: v_mov_b32_e32 v5, -1
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v7, -1
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; CHECK-NEXT: v_ashrrev_i32_e32 v0, v4, v8
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; CHECK-NEXT: v_ashrrev_i32_e32 v2, v6, v10
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; CHECK-NEXT: v_ashrrev_i32_e32 v4, v15, v12
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; CHECK-NEXT: v_ashrrev_i32_e32 v6, v17, v14
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%val = load <4 x i64>, ptr %arg0.ptr, !range !6, !noundef !{}
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%shift.amt = load <4 x i64>, ptr %arg1.ptr, !range !7, !noundef !{}
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%ashr = ashr <4 x i64> %val, %shift.amt
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ret <4 x i64> %ashr
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}
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; Ranges used when transformation is valid
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!0 = !{i64 -6000000000, i64 0}
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!1 = !{i64 32, i64 64}
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!2 = !{i64 -7000000000, i64 -1000}
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!3 = !{i64 38, i64 64}
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!4 = !{i64 -8000000000, i64 -2001}
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!5 = !{i64 38, i64 60}
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!6 = !{i64 -9000000000, i64 -3002}
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!7 = !{i64 38, i64 50}
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; Test that negative 64-bit values shifted by [2?-63] bits do NOT have
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; a hi-result created by moving an all-ones constant.
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define i64 @no_transform_scalar_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {
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; CHECK-LABEL: no_transform_scalar_ashr_metadata:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dwordx2 v[4:5], v[0:1]
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; CHECK-NEXT: flat_load_dword v6, v[2:3]
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_ashrrev_i64 v[0:1], v6, v[4:5]
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%val = load i64, ptr %arg0.ptr, !range !8, !noundef !{}
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%shift.amt = load i64, ptr %arg1.ptr, !range !9, !noundef !{}
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%ashr = ashr i64 %val, %shift.amt
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ret i64 %ashr
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}
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define <2 x i64> @no_transform_v2_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {
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; CHECK-LABEL: no_transform_v2_ashr_metadata:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
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; CHECK-NEXT: flat_load_dwordx4 v[8:11], v[2:3]
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_ashrrev_i64 v[0:1], v8, v[4:5]
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; CHECK-NEXT: v_ashrrev_i64 v[2:3], v10, v[6:7]
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%val = load <2 x i64>, ptr %arg0.ptr, !range !10, !noundef !{}
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%shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !11, !noundef !{}
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%ashr = ashr <2 x i64> %val, %shift.amt
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ret <2 x i64> %ashr
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}
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define <3 x i64> @no_transform_v3_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {
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; CHECK-LABEL: no_transform_v3_ashr_metadata:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[2:3]
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dwordx4 v[7:10], v[0:1]
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; CHECK-NEXT: flat_load_dwordx2 v[11:12], v[0:1] offset:16
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; CHECK-NEXT: flat_load_dword v5, v[2:3] offset:16
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_ashrrev_i64 v[0:1], v4, v[7:8]
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; CHECK-NEXT: v_ashrrev_i64 v[2:3], v6, v[9:10]
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; CHECK-NEXT: v_ashrrev_i64 v[4:5], v5, v[11:12]
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%val = load <3 x i64>, ptr %arg0.ptr, !range !12, !noundef !{}
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%shift.amt = load <3 x i64>, ptr %arg1.ptr, !range !13, !noundef !{}
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%ashr = ashr <3 x i64> %val, %shift.amt
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ret <3 x i64> %ashr
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}
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define <4 x i64> @no_transform_v4_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {
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; CHECK-LABEL: no_transform_v4_ashr_metadata:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[2:3]
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dwordx4 v[7:10], v[0:1]
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; CHECK-NEXT: flat_load_dwordx4 v[11:14], v[0:1] offset:16
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; CHECK-NEXT: flat_load_dwordx4 v[15:18], v[2:3] offset:16
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_ashrrev_i64 v[0:1], v4, v[7:8]
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; CHECK-NEXT: v_ashrrev_i64 v[2:3], v6, v[9:10]
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; CHECK-NEXT: v_ashrrev_i64 v[4:5], v15, v[11:12]
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; CHECK-NEXT: v_ashrrev_i64 v[6:7], v17, v[13:14]
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%val = load <4 x i64>, ptr %arg0.ptr, !range !14, !noundef !{}
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%shift.amt = load <4 x i64>, ptr %arg1.ptr, !range !15, !noundef !{}
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%ashr = ashr <4 x i64> %val, %shift.amt
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ret <4 x i64> %ashr
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}
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; Ranges used when transformation is invalid
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!8 = !{i64 -10000000000, i64 0}
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!9 = !{i64 29, i64 64}
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!10 = !{i64 -11000000000, i64 -1000}
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!11 = !{i64 28, i64 64}
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!12 = !{i64 -12000000000, i64 -2001}
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!13 = !{i64 27, i64 60}
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!14 = !{i64 -13000000000, i64 -3002}
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!15 = !{i64 26, i64 50}
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