derek.holloway
7502bf64a4
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173 lines
7.2 KiB
YAML
173 lines
7.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# REQUIRES: asserts
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-regalloc -misched-only-block=999 -start-before=machine-scheduler -stop-after=greedy,0 -o - %s | FileCheck %s
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# This run line is a total hack to get the live intervals to make it
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# to the verifier. This requires asserts to use
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# -misched-only-block. We use the scheduler only because -start-before
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# doesn't see si-optimize-exec-masking-pre-ra unless the scheduler is
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# part of the pass pipeline.
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---
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name: subreg_value_undef
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: subreg_value_undef
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $sgpr0_sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)
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; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 -1
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; CHECK-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, undef [[S_MOV_B32_]].sub0, implicit-def dead $scc
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; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_LOAD_DWORDX4_IMM]].sub0
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub1
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bb.0:
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liveins: $sgpr0_sgpr1
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)
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undef %2.sub1:sgpr_128 = S_MOV_B32 -1
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%3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %2.sub0, implicit $exec
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%4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec
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$vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc
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%2.sub1:sgpr_128 = COPY %1.sub0
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S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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bb.1:
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S_NOP 0, implicit %2.sub1
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...
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---
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name: needs_distribute_0
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: needs_distribute_0
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $sgpr0_sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)
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; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64_xexec = S_MOV_B32 -1
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; CHECK-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, [[S_MOV_B32_]].sub0, implicit-def dead $scc
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; CHECK-NEXT: dead [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64_xexec = COPY [[S_LOAD_DWORDX4_IMM]].sub0
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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bb.0:
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liveins: $sgpr0_sgpr1
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)
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undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1
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%3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2.sub0, implicit $exec
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%4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec
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$vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc
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%2.sub1:sreg_64_xexec = COPY %1.sub0
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S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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name: needs_distribute_1
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: needs_distribute_1
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $sgpr0_sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)
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; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64_xexec = S_MOV_B32 -1
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; CHECK-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, [[S_MOV_B32_]].sub0, implicit-def dead $scc
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; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64_xexec = COPY [[S_LOAD_DWORDX4_IMM]].sub0
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub1
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bb.0:
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liveins: $sgpr0_sgpr1
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)
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undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1
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%3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2.sub0, implicit $exec
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%4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec
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$vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc
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%2.sub1:sreg_64_xexec = COPY %1.sub0
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S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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bb.1:
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S_NOP 0, implicit %2.sub1
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...
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---
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name: needs_distribute_2
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: needs_distribute_2
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $sgpr0_sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)
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; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64_xexec = S_MOV_B32 -1
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; CHECK-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, [[S_MOV_B32_]].sub0, implicit-def dead $scc
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; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64_xexec = COPY [[S_LOAD_DWORDX4_IMM]].sub0
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
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bb.0:
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liveins: $sgpr0_sgpr1
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)
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undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1
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%3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2.sub0, implicit $exec
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%4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec
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$vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc
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%2.sub1:sreg_64_xexec = COPY %1.sub0
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S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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bb.1:
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S_NOP 0, implicit %2
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...
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---
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name: needs_distribute_3
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: needs_distribute_3
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $sgpr0_sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)
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; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64_xexec = S_MOV_B32 -1
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; CHECK-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, [[S_MOV_B32_]].sub0, implicit-def dead $scc
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; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64_xexec = COPY [[S_LOAD_DWORDX4_IMM]].sub0
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub0
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bb.0:
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liveins: $sgpr0_sgpr1
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)
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undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1
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%3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2.sub0, implicit $exec
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%4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec
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$vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc
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%2.sub1:sreg_64_xexec = COPY %1.sub0
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S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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bb.1:
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S_NOP 0, implicit %2.sub0
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...
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