derek.holloway
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35 lines
2.1 KiB
YAML
35 lines
2.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck %s
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# Test that the buildSpillLoadStore does correct calculations for Maxoffset in case of
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# spill instructions. Must emit offset within 13 bit signed number range.
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---
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name: test_spill_v6_offset_overflow
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, type: spill-slot, offset: 4084, size: 24, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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stack: []
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machineFunctionInfo:
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hasSpilledVGPRs: true
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stackPtrOffsetReg: '$sgpr32'
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
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; CHECK-LABEL: name: test_spill_v6_offset_overflow
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; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
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; CHECK-NEXT: $sgpr0 = S_ADD_I32 $sgpr32, 4084, implicit-def dead $scc
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; CHECK-NEXT: SCRATCH_STORE_DWORDX4_SADDR $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s128) into %fixed-stack.0, align 4, addrspace 5)
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; CHECK-NEXT: SCRATCH_STORE_DWORDX2_SADDR $vgpr4_vgpr5, killed $sgpr0, 16, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s64) into %fixed-stack.0 + 16, align 4, addrspace 5)
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; CHECK-NEXT: S_ENDPGM 0
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SI_SPILL_AV192_SAVE $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, %fixed-stack.0, $sgpr32, 0, implicit $exec :: (store (s192) into %fixed-stack.0, align 4, addrspace 5)
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S_ENDPGM 0
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...
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