derek.holloway
7502bf64a4
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205 lines
9.9 KiB
LLVM
205 lines
9.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s
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; Check that types where the store/allocation sizes don't match the type size
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; don't crash.
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define <7 x i9> @load_elem_i9_access_7xi9() {
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; CHECK-LABEL: @load_elem_i9_access_7xi9(
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; CHECK-NEXT: [[P:%.*]] = alloca <16 x i9>, align 1, addrspace(5)
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; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 4
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; CHECK-NEXT: [[L:%.*]] = load <7 x i9>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: ret <7 x i9> [[L]]
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;
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%p = alloca <16 x i9>, align 1, addrspace(5)
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%g = getelementptr i8, ptr addrspace(5) %p, i64 4
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%l = load <7 x i9>, ptr addrspace(5) %g, align 1
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ret <7 x i9> %l
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}
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define <8 x i1> @load_elem_i1_access_8xi1() {
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; CHECK-LABEL: @load_elem_i1_access_8xi1(
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; CHECK-NEXT: [[P:%.*]] = alloca <16 x i1>, align 1, addrspace(5)
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; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 4
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; CHECK-NEXT: [[L:%.*]] = load <8 x i1>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: ret <8 x i1> [[L]]
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;
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%p = alloca <16 x i1>, align 1, addrspace(5)
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%g = getelementptr i8, ptr addrspace(5) %p, i64 4
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%l = load <8 x i1>, ptr addrspace(5) %g, align 1
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ret <8 x i1> %l
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}
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define <3 x i1> @load_elem_i1_access_3xi1() {
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; CHECK-LABEL: @load_elem_i1_access_3xi1(
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; CHECK-NEXT: [[P:%.*]] = alloca <16 x i1>, align 1, addrspace(5)
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; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 4
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; CHECK-NEXT: [[L:%.*]] = load <3 x i1>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: ret <3 x i1> [[L]]
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;
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%p = alloca <16 x i1>, align 1, addrspace(5)
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%g = getelementptr i8, ptr addrspace(5) %p, i64 4
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%l = load <3 x i1>, ptr addrspace(5) %g, align 1
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ret <3 x i1> %l
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}
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define <3 x i1> @load_elem_i8_access_3xi1() {
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; CHECK-LABEL: @load_elem_i8_access_3xi1(
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; CHECK-NEXT: [[P:%.*]] = alloca <8 x i8>, align 1, addrspace(5)
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; CHECK-NEXT: store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) [[P]], align 1
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; CHECK-NEXT: [[G:%.*]] = getelementptr <4 x i8>, ptr addrspace(5) [[P]], i64 1
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; CHECK-NEXT: [[L:%.*]] = load <3 x i1>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: ret <3 x i1> [[L]]
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;
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%p = alloca <8 x i8>, align 1, addrspace(5)
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store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) %p, align 1
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%g = getelementptr <4 x i8>, ptr addrspace(5) %p, i64 1
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%l = load <3 x i1>, ptr addrspace(5) %g, align 1
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ret <3 x i1> %l
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}
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; This one is actually not problematic.
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define <8 x i1> @load_elem_i8_access_8xi1() {
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; CHECK-LABEL: @load_elem_i8_access_8xi1(
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; CHECK-NEXT: [[P:%.*]] = freeze <8 x i8> poison
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; CHECK-NEXT: ret <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>
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;
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%p = alloca <8 x i8>, align 1, addrspace(5)
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store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) %p, align 1
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%g = getelementptr <4 x i8>, ptr addrspace(5) %p, i64 1
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%l = load <8 x i1>, ptr addrspace(5) %g, align 1
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ret <8 x i1> %l
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}
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define <8 x i1> @storeload_elem_i1_access_8xi1() {
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; CHECK-LABEL: @storeload_elem_i1_access_8xi1(
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; CHECK-NEXT: [[P:%.*]] = alloca <16 x i1>, align 1, addrspace(5)
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; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 4
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; CHECK-NEXT: store <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: [[L:%.*]] = load <8 x i1>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: ret <8 x i1> [[L]]
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;
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%p = alloca <16 x i1>, align 1, addrspace(5)
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%g = getelementptr i8, ptr addrspace(5) %p, i64 4
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store <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, ptr addrspace(5) %g, align 1
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%l = load <8 x i1>, ptr addrspace(5) %g, align 1
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ret <8 x i1> %l
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}
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define <3 x i1> @storeload_elem_i1_access_3xi1() {
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; CHECK-LABEL: @storeload_elem_i1_access_3xi1(
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; CHECK-NEXT: [[P:%.*]] = alloca <16 x i1>, align 1, addrspace(5)
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; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 4
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; CHECK-NEXT: store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: [[L:%.*]] = load <3 x i1>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: ret <3 x i1> [[L]]
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;
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%p = alloca <16 x i1>, align 1, addrspace(5)
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%g = getelementptr i8, ptr addrspace(5) %p, i64 4
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store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) %g, align 1
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%l = load <3 x i1>, ptr addrspace(5) %g, align 1
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ret <3 x i1> %l
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}
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define <3 x i1> @storeload_elem_i8_access_3xi1() {
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; CHECK-LABEL: @storeload_elem_i8_access_3xi1(
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; CHECK-NEXT: [[P:%.*]] = alloca <8 x i8>, align 1, addrspace(5)
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; CHECK-NEXT: store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) [[P]], align 1
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; CHECK-NEXT: [[G:%.*]] = getelementptr <4 x i8>, ptr addrspace(5) [[P]], i64 1
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; CHECK-NEXT: store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: [[L:%.*]] = load <3 x i1>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: ret <3 x i1> [[L]]
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;
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%p = alloca <8 x i8>, align 1, addrspace(5)
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store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) %p, align 1
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%g = getelementptr <4 x i8>, ptr addrspace(5) %p, i64 1
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store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) %g, align 1
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%l = load <3 x i1>, ptr addrspace(5) %g, align 1
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ret <3 x i1> %l
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}
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; This one is actually not problematic.
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define <8 x i1> @storeload_elem_i8_access_8xi1() {
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; CHECK-LABEL: @storeload_elem_i8_access_8xi1(
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; CHECK-NEXT: [[P:%.*]] = freeze <8 x i8> poison
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; CHECK-NEXT: ret <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>
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;
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%p = alloca <8 x i8>, align 1, addrspace(5)
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store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) %p, align 1
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%g = getelementptr <4 x i8>, ptr addrspace(5) %p, i64 1
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store <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, ptr addrspace(5) %g, align 1
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%l = load <8 x i1>, ptr addrspace(5) %g, align 1
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ret <8 x i1> %l
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}
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define <8 x i1> @array_of_vec_elem_i1_access_8xi1() {
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; CHECK-LABEL: @array_of_vec_elem_i1_access_8xi1(
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; CHECK-NEXT: [[P:%.*]] = alloca [2 x <16 x i1>], align 1, addrspace(5)
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; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 4
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; CHECK-NEXT: store <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: [[L:%.*]] = load <8 x i1>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: ret <8 x i1> [[L]]
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;
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%p = alloca [2 x <16 x i1>], align 1, addrspace(5)
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%g = getelementptr i8, ptr addrspace(5) %p, i64 4
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store <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, ptr addrspace(5) %g, align 1
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%l = load <8 x i1>, ptr addrspace(5) %g, align 1
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ret <8 x i1> %l
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}
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define <3 x i1> @array_of_vec_elem_i1_access_3xi1() {
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; CHECK-LABEL: @array_of_vec_elem_i1_access_3xi1(
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; CHECK-NEXT: [[P:%.*]] = alloca [2 x <16 x i1>], align 1, addrspace(5)
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; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 4
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; CHECK-NEXT: store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: [[L:%.*]] = load <3 x i1>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: ret <3 x i1> [[L]]
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;
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%p = alloca [2 x <16 x i1>], align 1, addrspace(5)
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%g = getelementptr i8, ptr addrspace(5) %p, i64 4
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store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) %g, align 1
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%l = load <3 x i1>, ptr addrspace(5) %g, align 1
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ret <3 x i1> %l
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}
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define <3 x i1> @array_of_vec_elem_i8_access_3xi1() {
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; CHECK-LABEL: @array_of_vec_elem_i8_access_3xi1(
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; CHECK-NEXT: [[P:%.*]] = alloca [2 x <8 x i8>], align 1, addrspace(5)
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; CHECK-NEXT: store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) [[P]], align 1
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; CHECK-NEXT: [[G:%.*]] = getelementptr <4 x i8>, ptr addrspace(5) [[P]], i64 1
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; CHECK-NEXT: store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: [[L:%.*]] = load <3 x i1>, ptr addrspace(5) [[G]], align 1
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; CHECK-NEXT: ret <3 x i1> [[L]]
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;
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%p = alloca [2 x <8 x i8>], align 1, addrspace(5)
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store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) %p, align 1
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%g = getelementptr <4 x i8>, ptr addrspace(5) %p, i64 1
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store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) %g, align 1
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%l = load <3 x i1>, ptr addrspace(5) %g, align 1
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ret <3 x i1> %l
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}
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; This one is actually not problematic.
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define <8 x i1> @array_of_vec_elem_i8_access_8xi1() {
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; CHECK-LABEL: @array_of_vec_elem_i8_access_8xi1(
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; CHECK-NEXT: [[P:%.*]] = freeze <16 x i8> poison
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> [[P]], i8 1, i32 0
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x i8> [[TMP1]], i8 2, i32 1
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> [[TMP2]], i8 3, i32 2
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> [[TMP3]], i8 4, i32 3
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x i8> [[TMP4]], i8 5, i32 4
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x i8> [[TMP5]], i8 6, i32 5
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; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[TMP6]], i8 7, i32 6
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; CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x i8> [[TMP7]], i8 8, i32 7
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; CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 5, i32 4
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; CHECK-NEXT: ret <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>
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;
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%p = alloca [2 x <8 x i8>], align 1, addrspace(5)
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store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) %p, align 1
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%g = getelementptr <4 x i8>, ptr addrspace(5) %p, i64 1
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store <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, ptr addrspace(5) %g, align 1
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%l = load <8 x i1>, ptr addrspace(5) %g, align 1
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ret <8 x i1> %l
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}
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