derek.holloway
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154 lines
7.1 KiB
LLVM
154 lines
7.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s
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declare void @llvm.amdgcn.global.load.async.to.lds.b128(ptr addrspace(1), ptr addrspace(3), i32, i32)
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declare i32 @llvm.amdgcn.workitem.id.x()
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@lds = addrspace(3) global [1024 x i8] poison, align 16
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; Test when there is a positive offset value
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define amdgpu_kernel void @promote_async_load_offset_negative(ptr addrspace(1) %src) {
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; GFX1250-LABEL: promote_async_load_offset_negative:
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; GFX1250: ; %bb.0: ; %entry
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
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; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX1250-NEXT: v_mov_b32_e32 v1, 0
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; GFX1250-NEXT: s_mov_b64 s[2:3], 0xffffffffffffff00
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; GFX1250-NEXT: v_add_nc_u32_e64 v4, 0xfffffe00, 0
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
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; GFX1250-NEXT: v_add_nc_u32_e32 v0, 0x100, v0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1]
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[2:3]
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; GFX1250-NEXT: global_load_async_to_lds_b128 v1, v0, s[0:1]
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; GFX1250-NEXT: s_clause 0x1
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; GFX1250-NEXT: global_load_async_to_lds_b128 v4, v[2:3], off offset:512
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; GFX1250-NEXT: global_load_async_to_lds_b128 v1, v[2:3], off
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; GFX1250-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.offset = shl i32 %tid, 0
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%lds.gep = getelementptr i8, ptr addrspace(3) @lds, i32 0
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; First load at base + 256
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%offset0 = add i32 256, %gep.offset
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%zext0 = zext i32 %offset0 to i64
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%gep0 = getelementptr i8, ptr addrspace(1) %src, i64 %zext0
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call void @llvm.amdgcn.global.load.async.to.lds.b128(ptr addrspace(1) %gep0, ptr addrspace(3) %lds.gep, i32 0, i32 0)
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; Second load at base + 512 (+512 from 0)
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%offset1 = add i32 512, %gep.offset
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%zext1 = zext i32 %offset1 to i64
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%gep1 = getelementptr i8, ptr addrspace(1) %src, i64 %zext1
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call void @llvm.amdgcn.global.load.async.to.lds.b128(ptr addrspace(1) %gep1, ptr addrspace(3) %lds.gep, i32 0, i32 0)
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; Final load at base + 0
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%offset2 = add i32 0, %gep.offset
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%zext2 = zext i32 %offset2 to i64
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%gep2 = getelementptr i8, ptr addrspace(1) %src, i64 %zext2
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call void @llvm.amdgcn.global.load.async.to.lds.b128(ptr addrspace(1) %gep2, ptr addrspace(3) %lds.gep, i32 0, i32 0)
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ret void
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}
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; Test when there is a negative offset value
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define amdgpu_kernel void @promote_async_load_offset_positive(ptr addrspace(1) %src) {
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; GFX1250-LABEL: promote_async_load_offset_positive:
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; GFX1250: ; %bb.0: ; %entry
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
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; GFX1250-NEXT: v_mov_b32_e32 v1, 0
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; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX1250-NEXT: v_add_nc_u32_e64 v4, 0xffffff00, 0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1]
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; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], 0x100, v[2:3]
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; GFX1250-NEXT: global_load_async_to_lds_b128 v1, v0, s[0:1]
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; GFX1250-NEXT: s_clause 0x1
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; GFX1250-NEXT: global_load_async_to_lds_b128 v1, v[2:3], off
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; GFX1250-NEXT: global_load_async_to_lds_b128 v4, v[2:3], off offset:256
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; GFX1250-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.offset = shl i32 %tid, 0
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%lds.gep = getelementptr i8, ptr addrspace(3) @lds, i32 0
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; First load at base + 0
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%offset2 = add i32 0, %gep.offset
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%zext2 = zext i32 %offset2 to i64
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%gep2 = getelementptr i8, ptr addrspace(1) %src, i64 %zext2
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call void @llvm.amdgcn.global.load.async.to.lds.b128(ptr addrspace(1) %gep2, ptr addrspace(3) %lds.gep, i32 0, i32 0)
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; Second load at base + 256 (-256 from 512)
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%offset0 = add i32 256, %gep.offset
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%zext0 = zext i32 %offset0 to i64
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%gep0 = getelementptr i8, ptr addrspace(1) %src, i64 %zext0
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call void @llvm.amdgcn.global.load.async.to.lds.b128(ptr addrspace(1) %gep0, ptr addrspace(3) %lds.gep, i32 0, i32 0)
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; Final load at base + 512
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%offset1 = add i32 512, %gep.offset
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%zext1 = zext i32 %offset1 to i64
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%gep1 = getelementptr i8, ptr addrspace(1) %src, i64 %zext1
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call void @llvm.amdgcn.global.load.async.to.lds.b128(ptr addrspace(1) %gep1, ptr addrspace(3) %lds.gep, i32 0, i32 0)
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ret void
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}
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; Same as promote_async_load_offset_negative above, but for async stores. The
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; LDS address is in vdata instead of vdst, so this tests that
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; updateAsyncLDSAddress corrects the right operand.
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define amdgpu_kernel void @promote_async_store_offset_negative(ptr addrspace(1) %dst) {
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; GFX1250-LABEL: promote_async_store_offset_negative:
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; GFX1250: ; %bb.0: ; %entry
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
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; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX1250-NEXT: v_mov_b32_e32 v1, 0
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; GFX1250-NEXT: s_mov_b64 s[2:3], 0xffffffffffffff00
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; GFX1250-NEXT: v_add_nc_u32_e64 v4, 0xfffffe00, 0
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
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; GFX1250-NEXT: v_add_nc_u32_e32 v0, 0x100, v0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1]
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[2:3]
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; GFX1250-NEXT: global_store_async_from_lds_b128 v0, v1, s[0:1]
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; GFX1250-NEXT: s_clause 0x1
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; GFX1250-NEXT: global_store_async_from_lds_b128 v[2:3], v4, off offset:512
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; GFX1250-NEXT: global_store_async_from_lds_b128 v[2:3], v1, off
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; GFX1250-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.offset = shl i32 %tid, 0
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%lds.gep = getelementptr i8, ptr addrspace(3) @lds, i32 0
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; First store at base + 256
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%offset0 = add i32 256, %gep.offset
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%zext0 = zext i32 %offset0 to i64
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%gep0 = getelementptr i8, ptr addrspace(1) %dst, i64 %zext0
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call void @llvm.amdgcn.global.store.async.from.lds.b128(ptr addrspace(1) %gep0, ptr addrspace(3) %lds.gep, i32 0, i32 0)
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; Second store at base + 512 (+512 from 0)
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%offset1 = add i32 512, %gep.offset
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%zext1 = zext i32 %offset1 to i64
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%gep1 = getelementptr i8, ptr addrspace(1) %dst, i64 %zext1
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call void @llvm.amdgcn.global.store.async.from.lds.b128(ptr addrspace(1) %gep1, ptr addrspace(3) %lds.gep, i32 0, i32 0)
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; Final store at base + 0
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%offset2 = add i32 0, %gep.offset
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%zext2 = zext i32 %offset2 to i64
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%gep2 = getelementptr i8, ptr addrspace(1) %dst, i64 %zext2
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call void @llvm.amdgcn.global.store.async.from.lds.b128(ptr addrspace(1) %gep2, ptr addrspace(3) %lds.gep, i32 0, i32 0)
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ret void
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}
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