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194 lines
7.0 KiB
YAML
194 lines
7.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
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#
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---
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# the COPY can be coalesced based on subregister liveness
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name: subrange_coalesce_liveout
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: subrange_coalesce_liveout
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: liveins: $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[COPY]], 0, 0, implicit $exec
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; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.2(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]].sub0:vreg_128 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub0, [[GLOBAL_LOAD_DWORDX4_]].sub1, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[GLOBAL_LOAD_DWORDX4_]].sub2, [[GLOBAL_LOAD_DWORDX4_]].sub0, implicit $exec
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; GCN-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $vgpr0_vgpr1
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%0:vreg_64 = COPY $vgpr0_vgpr1
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%1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec
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%2:vgpr_32 = COPY %1.sub0
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.2
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%2:vgpr_32 = V_AND_B32_e64 %1.sub0, %1.sub1, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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%4:vgpr_32 = V_ADD_U32_e32 %1.sub2, %2, implicit $exec
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S_ENDPGM 0
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...
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---
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# early-clobber stops the coalescer from coalescing the COPY
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name: subrange_coalesce_early_clobber
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: subrange_coalesce_early_clobber
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: liveins: $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[COPY]], 0, 0, implicit $exec
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0
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; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.2(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: early-clobber [[COPY1]]:vgpr_32 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub0, [[GLOBAL_LOAD_DWORDX4_]].sub2, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[GLOBAL_LOAD_DWORDX4_]].sub2, [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $vgpr0_vgpr1
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%0:vreg_64 = COPY $vgpr0_vgpr1
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%1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec
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%2:vgpr_32 = COPY %1.sub0
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.2
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early-clobber %2:vgpr_32 = V_AND_B32_e64 %1.sub0, %1.sub2, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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%4:vgpr_32 = V_ADD_U32_e32 %1.sub2, %2, implicit $exec
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S_ENDPGM 0
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...
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---
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# non-conflict lane(sub1) was redefined, coalescable
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name: subrange_coalesce_unrelated_sub_redefined
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: subrange_coalesce_unrelated_sub_redefined
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: liveins: $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[COPY]], 0, 0, implicit $exec
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; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.2(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]].sub0:vreg_128 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub0, [[GLOBAL_LOAD_DWORDX4_]].sub1, implicit $exec
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; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]].sub1:vreg_128 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub0, [[GLOBAL_LOAD_DWORDX4_]].sub0, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[GLOBAL_LOAD_DWORDX4_]].sub1, [[GLOBAL_LOAD_DWORDX4_]].sub0, implicit $exec
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; GCN-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $vgpr0_vgpr1
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%0:vreg_64 = COPY $vgpr0_vgpr1
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%1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec
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%2:vgpr_32 = COPY %1.sub0
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.2
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%2:vgpr_32 = V_AND_B32_e64 %1.sub0, %1.sub1, implicit $exec
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%1.sub1:vreg_128 = V_AND_B32_e64 %2, %2, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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%4:vgpr_32 = V_ADD_U32_e32 %1.sub1, %2, implicit $exec
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S_ENDPGM 0
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...
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---
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# Another complex example showing the capability of resolving lane conflict
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# based on subranges.
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name: subrange_coalesce_complex_pattern
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: subrange_coalesce_complex_pattern
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: liveins: $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[COPY]], 0, 0, implicit $exec
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; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]].sub0:vreg_128 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub1, [[GLOBAL_LOAD_DWORDX4_]].sub0, implicit $exec
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; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]].sub2:vreg_128 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub0, [[GLOBAL_LOAD_DWORDX4_]].sub0, implicit $exec
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; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[GLOBAL_LOAD_DWORDX4_]].sub1, [[GLOBAL_LOAD_DWORDX4_]].sub2, implicit $exec
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; GCN-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $vgpr0_vgpr1
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%0:vreg_64 = COPY $vgpr0_vgpr1
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%1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec
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%2:vgpr_32 = COPY %1.sub0
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.1, %bb.2
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%2:vgpr_32 = V_AND_B32_e64 %1.sub1, %2, implicit $exec
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%1.sub2:vreg_128 = V_AND_B32_e64 %2, %2, implicit $exec
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S_CBRANCH_EXECZ %bb.1, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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%4:vgpr_32 = V_ADD_U32_e32 %1.sub1, %1.sub2, implicit $exec
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S_ENDPGM 0
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...
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