derek.holloway
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57 lines
3.0 KiB
YAML
57 lines
3.0 KiB
YAML
# REQUIRES: asserts
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -start-before=machine-scheduler -stop-after=greedy,2 -stress-regalloc=4 -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s
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--- |
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define amdgpu_kernel void @no_sched_metric_due_to_spills() #0 {
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ret void
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}
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attributes #0 = { "amdgpu-flat-work-group-size"="1,256" }
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...
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# This test checks for the following scenario: Unclustered high-RP-reschedule
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# stage raises the occupancy target temporarily but no region gets scheduled
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# because of constraints. Then, DAG and MFI min-occupancy should not be changed
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# at the end of the unclustered schedule stage.
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# CHECK: Retrying function scheduling without clustering. Aggressively try to reduce register pressure to achieve occupancy 5.
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# CHECK: Unclustered High Register Pressure Reschedule: No regions scheduled, min occupancy stays at 4, MFI occupancy stays at 4.
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---
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name: no_sched_metric_due_to_spills
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tracksRegLiveness: true
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machineFunctionInfo:
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stackPtrOffsetReg: '$sgpr32'
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occupancy: 4
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1, $sgpr15
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%0:sgpr_32 = COPY $sgpr15
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%2:vgpr_32 = COPY $vgpr0
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%3:sgpr_128 = S_LOAD_DWORDX4_IMM %1, 0, 0 :: (dereferenceable invariant load (s128), addrspace 4)
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undef %4.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 16, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
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%5:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 32, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
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%6:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 64, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
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%7:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 84, 0 :: (dereferenceable invariant load (s32), addrspace 4)
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%8:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 112, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
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%9:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 128, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
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%10:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 176, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
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%11:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 192, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
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%12:sreg_64_xexec = S_LOAD_DWORDX2_IMM %1, 216, 0 :: (dereferenceable invariant load (s64), addrspace 4)
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%13:sreg_32 = S_ADD_I32 %12.sub0, 127, implicit-def dead $scc
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%14:sreg_32 = S_ASHR_I32 %13, 31, implicit-def dead $scc
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%15:sreg_32 = S_LSHR_B32 %14, 25, implicit-def dead $scc
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%16:sreg_32 = S_ADD_I32 %13, %15, implicit-def dead $scc
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%17:sreg_32 = S_ASHR_I32 %16, 7, implicit-def dead $scc
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%18:sreg_32 = S_ADD_I32 %12.sub1, 255, implicit-def dead $scc
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%19:sreg_32 = S_ASHR_I32 %18, 31, implicit-def dead $scc
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%20:sreg_32 = S_LSHR_B32 %19, 24, implicit-def dead $scc
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%21:sreg_32 = S_ADD_I32 %18, %20, implicit-def dead $scc
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%22:sreg_32 = S_ASHR_I32 %21, 8, implicit-def dead $scc
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%23:sreg_32 = nsw S_MUL_I32 %22, %17
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%24:sreg_32 = S_ASHR_I32 %0, 31, implicit-def dead $scc
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S_ENDPGM 0
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...
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