derek.holloway
7502bf64a4
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20 lines
860 B
LLVM
20 lines
860 B
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s
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; Copy VGPR -> SGPR used twice as an instruction operand, which is then
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; used in an REG_SEQUENCE that also needs to be handled.
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; SI-LABEL: {{^}}test_dup_operands:
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; SI: v_add_{{[iu]}}32_e32
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define amdgpu_kernel void @test_dup_operands(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) {
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%a = load <2 x i32>, ptr addrspace(1) %in
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%lo = extractelement <2 x i32> %a, i32 0
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%hi = extractelement <2 x i32> %a, i32 1
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%add = add i32 %lo, %lo
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%vec0 = insertelement <2 x i32> poison, i32 %add, i32 0
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%vec1 = insertelement <2 x i32> %vec0, i32 %hi, i32 1
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store <2 x i32> %vec1, ptr addrspace(1) %out, align 8
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ret void
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}
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