derek.holloway
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41 lines
1.5 KiB
LLVM
41 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck %s
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; Check transformation shl (or|add x, c2), c1 => or|add (shl x, c1), (c2 << c1)
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; Only one shift if expected, GEP shall not produce a separate shift
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; CHECK-LABEL: {{^}}add_const_offset:
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; CHECK: v_lshlrev_b32_e32 v[[SHL:[0-9]+]], 4, v0
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; CHECK: v_add_u32_e32 v[[ADD:[0-9]+]], vcc, 0xc80, v[[SHL]]
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; CHECK-NOT: v_lshl
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; CHECK: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADD]]
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; CHECK: load_dword v{{[0-9]+}}, v[[[ADDRLO]]:
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define amdgpu_kernel void @add_const_offset(ptr addrspace(1) nocapture %arg) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%add = add i32 %id, 200
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%shl = shl i32 %add, 2
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%ptr = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %shl
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%val = load i32, ptr addrspace(1) %ptr, align 4
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store i32 %val, ptr addrspace(1) %arg, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}or_const_offset:
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; CHECK: v_lshlrev_b32_e32 v[[SHL:[0-9]+]], 4, v0
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; CHECK: v_or_b32_e32 v[[OR:[0-9]+]], 0x1000, v[[SHL]]
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; CHECK-NOT: v_lshl
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; CHECK: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[OR]]
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; CHECK: load_dword v{{[0-9]+}}, v[[[ADDRLO]]:
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define amdgpu_kernel void @or_const_offset(ptr addrspace(1) nocapture %arg) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%add = or i32 %id, 256
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%shl = shl i32 %add, 2
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%ptr = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %shl
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%val = load i32, ptr addrspace(1) %ptr, align 4
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store i32 %val, ptr addrspace(1) %arg, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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