derek.holloway
7502bf64a4
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40 lines
1.7 KiB
LLVM
40 lines
1.7 KiB
LLVM
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa --amdgpu-annotate-uniform < %s | FileCheck -check-prefix=OPT %s
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; "load vaddr" depends on the store, so we should not mark vaddr as amdgpu.noclobber.
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; OPT-LABEL: @store_clobbers_load(
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; OPT: %zero = load <4 x i32>, ptr addrspace(1) %input, align 16{{$}}
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define amdgpu_kernel void @store_clobbers_load(ptr addrspace(1) %input, ptr addrspace(1) %out, i32 %index) {
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entry:
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store i32 0, ptr addrspace(1) %input
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%zero = load <4 x i32>, ptr addrspace(1) %input, align 16
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%one = insertelement <4 x i32> %zero, i32 1, i32 1
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%two = insertelement <4 x i32> %one, i32 2, i32 2
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%three = insertelement <4 x i32> %two, i32 3, i32 3
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store <4 x i32> %three, ptr addrspace(1) %input, align 16
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%rslt = extractelement <4 x i32> %three, i32 %index
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store i32 %rslt, ptr addrspace(1) %out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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@lds0 = addrspace(3) global [512 x i32] poison, align 4
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; To check that %arrayidx0 is not marked as amdgpu.noclobber.
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; OPT-LABEL: @atomicrmw_clobbers_load(
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; OPT: %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds0, i32 0, i32 %idx.0
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; OPT-NEXT: %val = atomicrmw xchg ptr addrspace(3) %arrayidx0, i32 3 seq_cst
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define amdgpu_kernel void @atomicrmw_clobbers_load(ptr addrspace(1) %out0, ptr addrspace(1) %out1) {
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds0, i32 0, i32 %idx.0
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%val = atomicrmw xchg ptr addrspace(3) %arrayidx0, i32 3 seq_cst
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%load = load i32, ptr addrspace(3) %arrayidx0, align 4
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store i32 %val, ptr addrspace(1) %out0, align 4
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store i32 %load, ptr addrspace(1) %out1, align 4
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ret void
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}
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