derek.holloway
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63 lines
2.2 KiB
LLVM
63 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefix=GCN %s
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define void @test(i1 %c0) #1 {
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; Clean up the unreachable blocks introduced with LowerSwitch pass.
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; This test ensures that, in the pass flow, UnreachableBlockElim pass
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; follows the LowerSwitch. Otherwise, this testcase will crash
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; immediately after the instruction selection due to the incomplete
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; PHI node in an MBB whose incoming values were never codegenerated.
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;
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; GCN-LABEL: name: test
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; GCN: bb.{{[0-9]+}}.entry:
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; GCN: bb.{{[0-9]+}}.Flow1:
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; GCN: bb.{{[0-9]+}}.entry.true.blk:
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; GCN: bb.{{[0-9]+}}.entry.false.blk:
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; GCN: bb.{{[0-9]+}}.switch.blk:
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; GCN-NOT: bb.{{[0-9]+}}.preheader.blk
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; GCN-NOT: bb.{{[0-9]+}}.pre.false.blk:
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; GCN-NOT: bb.{{[0-9]+}}.unreach.blk:
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; GCN-NOT: PHI
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; GCN: bb.{{[0-9]+}}.Flow:
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; GCN: bb.{{[0-9]+}}.UnifiedReturnBlock:
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entry:
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%idx = tail call i32 @llvm.amdgcn.workitem.id.x() #0
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br i1 %c0, label %entry.true.blk, label %entry.false.blk
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entry.true.blk: ; preds = %entry
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%exit.cmp = icmp ult i32 %idx, 3
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br i1 %exit.cmp, label %switch.blk, label %exit
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entry.false.blk: ; preds = %entry
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unreachable
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switch.blk: ; preds = %entry.true.blk
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switch i32 %idx, label %preheader.blk [
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i32 0, label %exit
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i32 1, label %exit
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i32 2, label %exit
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]
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preheader.blk: ; preds = %switch.blk
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%pre.exit = icmp ult i32 %idx, 5
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br i1 %pre.exit, label %unreach.blk, label %pre.false.blk
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pre.false.blk: ; preds = %preheader.blk
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%call.pre.false = tail call i32 @func(i32 %idx) #0
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br label %unreach.blk
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unreach.blk: ; preds = %preheader.blk, %pre.false.blk
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%phi.val = phi i32 [ %call.pre.false, %pre.false.blk ], [ poison, %preheader.blk ]
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store i32 %phi.val, ptr poison
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unreachable
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exit: ; preds = %switch.blk
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i32 @func(i32)#0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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