derek.holloway
7502bf64a4
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24 lines
1.0 KiB
LLVM
24 lines
1.0 KiB
LLVM
;RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s
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;CHECK: TEX
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;CHECK-NEXT: ALU
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define amdgpu_vs void @test(<4 x float> inreg %reg0) {
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%1 = extractelement <4 x float> %reg0, i32 0
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%2 = extractelement <4 x float> %reg0, i32 1
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%3 = extractelement <4 x float> %reg0, i32 2
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%4 = extractelement <4 x float> %reg0, i32 3
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%5 = insertelement <4 x float> poison, float %1, i32 0
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%6 = insertelement <4 x float> %5, float %2, i32 1
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%7 = insertelement <4 x float> %6, float %3, i32 2
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%8 = insertelement <4 x float> %7, float %4, i32 3
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%9 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%10 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%11 = fadd <4 x float> %9, %10
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call void @llvm.r600.store.swizzle(<4 x float> %11, i32 0, i32 0)
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ret void
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}
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declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
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declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
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