derek.holloway
7502bf64a4
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184 lines
9.3 KiB
LLVM
184 lines
9.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950 %s
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; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250-TRUE16 %s
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; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250-FAKE16 %s
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; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX1300-TRUE16 %s
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; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX1300-FAKE16 %s
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define amdgpu_kernel void @v_ashr_pk_i8_i32(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 {
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; GFX950-LABEL: v_ashr_pk_i8_i32:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
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; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
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; GFX950-NEXT: v_mov_b32_e32 v0, 0
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; GFX950-NEXT: s_waitcnt lgkmcnt(0)
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; GFX950-NEXT: s_and_b32 s2, s2, 31
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; GFX950-NEXT: v_mov_b32_e32 v1, s1
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; GFX950-NEXT: v_mov_b32_e32 v2, s2
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; GFX950-NEXT: v_ashr_pk_i8_i32 v1, s0, v1, v2
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; GFX950-NEXT: global_store_short v0, v1, s[6:7]
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; GFX950-NEXT: s_endpgm
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;
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; GFX1250-TRUE16-LABEL: v_ashr_pk_i8_i32:
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; GFX1250-TRUE16: ; %bb.0:
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; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-TRUE16-NEXT: v_nop
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; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-TRUE16-NEXT: s_clause 0x1
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; GFX1250-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
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; GFX1250-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
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; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
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; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX1250-TRUE16-NEXT: s_and_b32 s2, s2, 31
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; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
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; GFX1250-TRUE16-NEXT: v_ashr_pk_i8_i32 v0.l, s0, s1, v0
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; GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
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; GFX1250-TRUE16-NEXT: s_endpgm
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;
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; GFX1250-FAKE16-LABEL: v_ashr_pk_i8_i32:
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; GFX1250-FAKE16: ; %bb.0:
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; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-FAKE16-NEXT: v_nop
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; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-FAKE16-NEXT: s_clause 0x1
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; GFX1250-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
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; GFX1250-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
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; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v1, 0
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; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GFX1250-FAKE16-NEXT: s_and_b32 s2, s2, 31
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; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, s2
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; GFX1250-FAKE16-NEXT: v_ashr_pk_i8_i32 v0, s0, s1, v0
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; GFX1250-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
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; GFX1250-FAKE16-NEXT: s_endpgm
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;
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; GFX1300-TRUE16-LABEL: v_ashr_pk_i8_i32:
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; GFX1300-TRUE16: ; %bb.0:
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; GFX1300-TRUE16-NEXT: s_clause 0x1
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; GFX1300-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
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; GFX1300-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv
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; GFX1300-TRUE16-NEXT: v_mov_b32_e32 v1, 0
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; GFX1300-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX1300-TRUE16-NEXT: s_and_b32 s2, s2, 31
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; GFX1300-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1300-TRUE16-NEXT: v_mov_b32_e32 v0, s2
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; GFX1300-TRUE16-NEXT: v_ashr_pk_i8_i32 v0.l, s0, s1, v0
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; GFX1300-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
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; GFX1300-TRUE16-NEXT: s_endpgm
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;
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; GFX1300-FAKE16-LABEL: v_ashr_pk_i8_i32:
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; GFX1300-FAKE16: ; %bb.0:
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; GFX1300-FAKE16-NEXT: s_clause 0x1
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; GFX1300-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
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; GFX1300-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv
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; GFX1300-FAKE16-NEXT: v_mov_b32_e32 v1, 0
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; GFX1300-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GFX1300-FAKE16-NEXT: s_and_b32 s2, s2, 31
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; GFX1300-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1300-FAKE16-NEXT: v_mov_b32_e32 v0, s2
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; GFX1300-FAKE16-NEXT: v_ashr_pk_i8_i32 v0, s0, s1, v0
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; GFX1300-FAKE16-NEXT: global_store_b16 v1, v0, s[4:5]
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; GFX1300-FAKE16-NEXT: s_endpgm
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%insert.0 = insertelement <2 x i32> poison, i32 %src0, i64 0
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%build_vector = insertelement <2 x i32> %insert.0, i32 %src1, i64 1
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%src2.clamp = and i32 %src2, 31
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%insert.1 = insertelement <2 x i32> poison, i32 %src2.clamp, i64 0
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%src2.broadcast = shufflevector <2 x i32> %insert.1, <2 x i32> poison, <2 x i32> zeroinitializer
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%ashr = ashr <2 x i32> %build_vector, %src2.broadcast
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%sat.low = tail call <2 x i32> @llvm.smax.v2i32(<2 x i32> %ashr, <2 x i32> <i32 -128, i32 -128>)
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%sat.hi = tail call <2 x i32> @llvm.smin.v2i32(<2 x i32> %sat.low, <2 x i32> <i32 127, i32 127>)
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%trunc = trunc nsw <2 x i32> %sat.hi to <2 x i8>
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%ret = bitcast <2 x i8> %trunc to i16
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store i16 %ret, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @v_ashr_pk_u8_i32(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 {
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; GFX950-LABEL: v_ashr_pk_u8_i32:
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; GFX950: ; %bb.0:
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; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
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; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
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; GFX950-NEXT: v_mov_b32_e32 v0, 0
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; GFX950-NEXT: s_waitcnt lgkmcnt(0)
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; GFX950-NEXT: s_and_b32 s2, s2, 31
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; GFX950-NEXT: v_mov_b32_e32 v1, s1
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; GFX950-NEXT: v_mov_b32_e32 v2, s2
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; GFX950-NEXT: v_ashr_pk_u8_i32 v1, s0, v1, v2
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; GFX950-NEXT: global_store_short v0, v1, s[6:7]
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; GFX950-NEXT: s_endpgm
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;
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; GFX1250-TRUE16-LABEL: v_ashr_pk_u8_i32:
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; GFX1250-TRUE16: ; %bb.0:
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; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-TRUE16-NEXT: v_nop
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; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-TRUE16-NEXT: s_clause 0x1
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; GFX1250-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
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; GFX1250-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
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; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
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; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX1250-TRUE16-NEXT: s_and_b32 s2, s2, 31
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; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
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; GFX1250-TRUE16-NEXT: v_ashr_pk_u8_i32 v0.l, s0, s1, v0
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; GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
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; GFX1250-TRUE16-NEXT: s_endpgm
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;
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; GFX1250-FAKE16-LABEL: v_ashr_pk_u8_i32:
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; GFX1250-FAKE16: ; %bb.0:
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; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-FAKE16-NEXT: v_nop
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; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-FAKE16-NEXT: s_clause 0x1
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; GFX1250-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
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; GFX1250-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
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; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v1, 0
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; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GFX1250-FAKE16-NEXT: s_and_b32 s2, s2, 31
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; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, s2
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; GFX1250-FAKE16-NEXT: v_ashr_pk_u8_i32 v0, s0, s1, v0
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; GFX1250-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
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; GFX1250-FAKE16-NEXT: s_endpgm
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;
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; GFX1300-TRUE16-LABEL: v_ashr_pk_u8_i32:
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; GFX1300-TRUE16: ; %bb.0:
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; GFX1300-TRUE16-NEXT: s_clause 0x1
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; GFX1300-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
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; GFX1300-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv
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; GFX1300-TRUE16-NEXT: v_mov_b32_e32 v1, 0
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; GFX1300-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX1300-TRUE16-NEXT: s_and_b32 s2, s2, 31
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; GFX1300-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1300-TRUE16-NEXT: v_mov_b32_e32 v0, s2
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; GFX1300-TRUE16-NEXT: v_ashr_pk_u8_i32 v0.l, s0, s1, v0
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; GFX1300-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
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; GFX1300-TRUE16-NEXT: s_endpgm
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;
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; GFX1300-FAKE16-LABEL: v_ashr_pk_u8_i32:
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; GFX1300-FAKE16: ; %bb.0:
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; GFX1300-FAKE16-NEXT: s_clause 0x1
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; GFX1300-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
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; GFX1300-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv
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; GFX1300-FAKE16-NEXT: v_mov_b32_e32 v1, 0
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; GFX1300-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GFX1300-FAKE16-NEXT: s_and_b32 s2, s2, 31
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; GFX1300-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1300-FAKE16-NEXT: v_mov_b32_e32 v0, s2
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; GFX1300-FAKE16-NEXT: v_ashr_pk_u8_i32 v0, s0, s1, v0
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; GFX1300-FAKE16-NEXT: global_store_b16 v1, v0, s[4:5]
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; GFX1300-FAKE16-NEXT: s_endpgm
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%insert.0 = insertelement <2 x i32> poison, i32 %src0, i64 0
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%build_vector = insertelement <2 x i32> %insert.0, i32 %src1, i64 1
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%src2.clamp = and i32 %src2, 31
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%insert.1 = insertelement <2 x i32> poison, i32 %src2.clamp, i64 0
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%src2.broadcast = shufflevector <2 x i32> %insert.1, <2 x i32> poison, <2 x i32> zeroinitializer
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%ashr = ashr <2 x i32> %build_vector, %src2.broadcast
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%sat.low = tail call <2 x i32> @llvm.smax.v2i32(<2 x i32> %ashr, <2 x i32> <i32 0, i32 0>)
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%sat.hi = tail call <2 x i32> @llvm.smin.v2i32(<2 x i32> %sat.low, <2 x i32> <i32 255, i32 255>)
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%trunc = trunc nsw <2 x i32> %sat.hi to <2 x i8>
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%ret = bitcast <2 x i8> %trunc to i16
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store i16 %ret, ptr addrspace(1) %out
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ret void
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}
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