derek.holloway
7502bf64a4
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152 lines
7.5 KiB
YAML
152 lines
7.5 KiB
YAML
# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=machineverifier -filetype=null %s 2>&1 | FileCheck %s
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# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx90a --passes='machine-function(verify)' -filetype=null %s 2>&1 | FileCheck %s
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# Implicit uses are OK.
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---
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name: implicit_use
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body: |
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bb.0:
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$vgpr1_vgpr2 = IMPLICIT_DEF
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S_NOP 0, implicit $vgpr1_vgpr2
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%0:vreg_64 = IMPLICIT_DEF
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S_NOP 0, implicit %0
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%1:sreg_64_xexec = IMPLICIT_DEF
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%2:sreg_64_xexec = SI_CALL %1, 0, csr_amdgpu, implicit $vgpr1_vgpr2
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; noreg is OK
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DS_WRITE_B64_gfx9 $noreg, $noreg, 0, 0, implicit $exec
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...
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# The unaligned registers are allowed to exist, just not on any tuple instructions.
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---
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name: copy_like_generic
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body: |
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bb.0:
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$vgpr1_vgpr2 = IMPLICIT_DEF
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$vgpr3_vgpr4 = COPY $vgpr1_vgpr2
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%0:vreg_64 = IMPLICIT_DEF
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%1:vreg_64 = COPY %0
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...
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---
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name: mov_32_unaligned_super
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body: |
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bb.0:
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undef %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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%1:vgpr_32 = V_MOV_B32_e32 undef %2.sub1:vreg_64, implicit $exec
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...
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# Well-aligned subregister indexes are OK
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---
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name: aligned_sub_reg
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body: |
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bb.0:
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%0:vreg_64_align2 = IMPLICIT_DEF
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%1:vreg_128_align2 = IMPLICIT_DEF
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GLOBAL_STORE_DWORDX2 %0, %1.sub0_sub1, 0, 0, implicit $exec
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GLOBAL_STORE_DWORDX2 %0, %1.sub2_sub3, 0, 0, implicit $exec
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...
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---
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name: unaligned_registers
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr3_vgpr4_vgpr5_vgpr6
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%0:vreg_64_align2 = IMPLICIT_DEF
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%1:vreg_64 = IMPLICIT_DEF
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%2:vreg_96 = IMPLICIT_DEF
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%3:vreg_128 = IMPLICIT_DEF
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%4:areg_64 = IMPLICIT_DEF
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%5:vreg_128_align2 = IMPLICIT_DEF
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; Check virtual register uses
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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GLOBAL_STORE_DWORDX2 %0, %1, 0, 0, implicit $exec
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GLOBAL_STORE_DWORDX3 %0, %2, 0, 0, implicit $exec
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GLOBAL_STORE_DWORDX4 %0, %3, 0, 0, implicit $exec
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; Check virtual registers with subregisters
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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GLOBAL_STORE_DWORDX2 %0, %3.sub0_sub1, 0, 0, implicit $exec
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GLOBAL_STORE_DWORDX2 %0, %3.sub2_sub3, 0, 0, implicit $exec
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GLOBAL_STORE_DWORDX2 %0, %3.sub1_sub2, 0, 0, implicit $exec
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GLOBAL_STORE_DWORDX2 %0, %5.sub1_sub2, 0, 0, implicit $exec
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; Check physical register uses
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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GLOBAL_STORE_DWORDX2 $vgpr0_vgpr1, $vgpr3_vgpr4, 0, 0, implicit $exec
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GLOBAL_STORE_DWORDX3 $vgpr0_vgpr1, $vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec
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GLOBAL_STORE_DWORDX4 $vgpr0_vgpr1, $vgpr3_vgpr4_vgpr5_vgpr6, 0, 0, implicit $exec
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; Check virtual register defs
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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%6:vreg_64 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, implicit $exec
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%7:vreg_96 = GLOBAL_LOAD_DWORDX3 %0, 0, 0, implicit $exec
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%8:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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$vgpr1_vgpr2 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, implicit $exec
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$vgpr1_vgpr2_vgpr3 = GLOBAL_LOAD_DWORDX3 %0, 0, 0, implicit $exec
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$vgpr1_vgpr2_vgpr3_vgpr4 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec
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; Check AGPRs
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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%9:vgpr_32 = IMPLICIT_DEF
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%10:areg_64 = IMPLICIT_DEF
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%11:areg_128_align2 = IMPLICIT_DEF
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DS_WRITE_B64_gfx9 %9, %10, 0, 0, implicit $exec
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DS_WRITE_B64_gfx9 %9, %11.sub1_sub2, 0, 0, implicit $exec
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; Check aligned vgprs for FP32 Packed Math instructions.
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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%12:vreg_64 = IMPLICIT_DEF
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%13:vreg_64_align2 = IMPLICIT_DEF
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%14:areg_96_align2 = IMPLICIT_DEF
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$vgpr3_vgpr4 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
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$vgpr0_vgpr1 = V_PK_ADD_F32 0, %12, 11, %13, 0, 0, 0, 0, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = V_PK_ADD_F32 0, %13, 11, %12, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = V_PK_ADD_F32 0, %13, 11, %14.sub1_sub2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = V_PK_ADD_F32 0, %14.sub1_sub2, 11, %13, 0, 0, 0, 0, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = V_PK_MUL_F32 0, %12, 11, %13, 0, 0, 0, 0, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = V_PK_MUL_F32 0, %13, 11, %12, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = V_PK_MUL_F32 0, %13, 11, %14.sub1_sub2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = V_PK_MUL_F32 0, %14.sub1_sub2, 11, %13, 0, 0, 0, 0, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %12, 8, %13, 11, %14.sub0_sub1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %13, 8, %12, 11, %14.sub0_sub1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %13, 8, %13, 11, %14.sub1_sub2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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...
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# FIXME: Inline asm is not verified
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# ; Check inline asm
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# ; XCHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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# ; XCHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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# ; XCHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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# INLINEASM &"; use $0 ", sideeffect attdialect, reguse, $vgpr1_vgpr2
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# INLINEASM &"; use $0 ", sideeffect attdialect, reguse, %4
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# INLINEASM &"; use $0 ", sideeffect attdialect, reguse, %5.sub1_sub2
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