derek.holloway
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89 lines
3.2 KiB
LLVM
89 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx950 < %s | FileCheck %s
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declare void @llvm.amdgcn.sched.barrier(i32 %mask)
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declare void @llvm.amdgcn.load.to.lds(ptr %in, ptr addrspace(3) %lds_out, i32 %size, i32 %offset, i32 %aux)
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define amdgpu_kernel void @test_waitcnt(ptr addrspace(1) %global_buffer, ptr addrspace(3) %lds_buffer1, ptr addrspace(3) %lds_buffer2) #0 {
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; This test checks if SIInsertWaitcnts pass inserts S_WAITCNT VMCNT(0) before DS_READ
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; CHECK-LABEL: test_waitcnt:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_load_dword s6, s[0:1], 0x0
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; CHECK-NEXT: s_add_u32 s4, s0, 64
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; CHECK-NEXT: s_addc_u32 s5, s1, 0
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; CHECK-NEXT: s_mov_b32 m0, s2
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v3, s6
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; CHECK-NEXT: global_store_dword v0, v3, s[0:1] offset:64
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; CHECK-NEXT: global_load_lds_dword v0, s[4:5] offset:4
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; CHECK-NEXT: ; sched_barrier mask(0x00000000)
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; CHECK-NEXT: v_mov_b32_e32 v1, s2
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; CHECK-NEXT: v_mov_b32_e32 v2, s3
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; CHECK-NEXT: ds_write_b32 v1, v3
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; CHECK-NEXT: ds_write_b32 v2, v3
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; CHECK-NEXT: ; sched_barrier mask(0x00000000)
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; CHECK-NEXT: ds_read_b32 v1, v1
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_store_dword v0, v1, s[0:1] offset:16
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; CHECK-NEXT: global_store_dword v0, v3, s[0:1] offset:32
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; CHECK-NEXT: s_endpgm
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entry:
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; VMEM accesses with alias.scope
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%vmem_load = load i32, ptr addrspace(1) %global_buffer
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%gepvmem = getelementptr i32, ptr addrspace(1) %global_buffer, i32 16
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store i32 %vmem_load, ptr addrspace(1) %gepvmem, align 4, !alias.scope !0
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; Global to LDS load
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%gepvmem.ascast = addrspacecast ptr addrspace(1) %gepvmem to ptr
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call void @llvm.amdgcn.load.to.lds(ptr %gepvmem.ascast, ptr addrspace(3) %lds_buffer1, i32 4, i32 4, i32 0), !alias.scope !9, !noalias !14
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; Insert scheduling barrier
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call void @llvm.amdgcn.sched.barrier(i32 0)
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; DS_WRITEs with alias.scope and noalias
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store i32 %vmem_load, ptr addrspace(3) %lds_buffer1, align 4, !alias.scope !1, !noalias !12
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store i32 %vmem_load, ptr addrspace(3) %lds_buffer2, align 4, !alias.scope !6, !noalias !13
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; Insert scheduling barrier
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call void @llvm.amdgcn.sched.barrier(i32 0)
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; DS_READ with alias.scope missing
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%lds_load = load i32, ptr addrspace(3) %lds_buffer1, align 4, !noalias !12
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; VMEM write
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%gep = getelementptr i32, ptr addrspace(1) %global_buffer, i32 4
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%gep2 = getelementptr i32, ptr addrspace(1) %global_buffer, i32 8
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store i32 %lds_load, ptr addrspace(1) %gep, align 4, !alias.scope !0
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store i32 %vmem_load, ptr addrspace(1) %gep2, align 4, !alias.scope !0
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ret void
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}
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; VMEM alias domain and scope
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!5 = !{!"vmem.domain"}
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!4 = !{!"vmem.scope", !5}
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!0 = !{!4}
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; LDS alias domains and scopes
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!3 = !{!"lds1.domain"}
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!2 = !{!"lds1.scope", !3}
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!1 = !{!2}
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!8 = !{!"lds2.domain"}
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!7 = !{!"lds2.scope", !8}
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!6 = !{!7}
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!11 = !{!"lds1_off4.domain"}
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!10 = !{!"lds1_off4.scope", !11}
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!9 = !{!10}
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; Noalias lists
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!12 = !{!7, !10}
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!13 = !{!2, !10}
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!14 = !{!2, !7}
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attributes #0 = { nounwind }
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