derek.holloway
7502bf64a4
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385 lines
20 KiB
LLVM
385 lines
20 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1170 < %s | FileCheck %s --check-prefixes=GCN,GFX1170
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s --check-prefixes=GCN,GFX12
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define amdgpu_ps void @test_wmma_f32_16x16x16_f16_imm(<8 x half> %A, <8 x half> %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_f32_16x16x16_f16_imm:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_wmma_f32_16x16x16_f16 v[10:17], v[0:3], v[4:7], 1.0
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; GCN-NEXT: s_clause 0x1
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; GCN-NEXT: global_store_b128 v[8:9], v[14:17], off offset:16
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; GCN-NEXT: global_store_b128 v[8:9], v[10:13], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16.v8f32.v8f16(<8 x half> %A, <8 x half> %B, <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>)
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store <8 x float> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_f32_16x16x16_f16_imm_non_inlineable(<8 x half> %A, <8 x half> %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_f32_16x16x16_f16_imm_non_inlineable:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_mov_b32_e32 v10, 0x40400000
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
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; GCN-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v12, v10
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; GCN-NEXT: v_dual_mov_b32 v13, v10 :: v_dual_mov_b32 v14, v10
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; GCN-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v16, v10
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; GCN-NEXT: v_mov_b32_e32 v17, v10
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; GCN-NEXT: v_wmma_f32_16x16x16_f16 v[10:17], v[0:3], v[4:7], v[10:17]
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; GCN-NEXT: s_clause 0x1
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; GCN-NEXT: global_store_b128 v[8:9], v[14:17], off offset:16
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; GCN-NEXT: global_store_b128 v[8:9], v[10:13], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16.v8f32.v8f16(<8 x half> %A, <8 x half> %B, <8 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>)
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store <8 x float> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_f32_16x16x16_bf16_imm(<8 x i16> %A, <8 x i16> %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_f32_16x16x16_bf16_imm:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_wmma_f32_16x16x16_bf16 v[10:17], v[0:3], v[4:7], 1.0
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; GCN-NEXT: s_clause 0x1
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; GCN-NEXT: global_store_b128 v[8:9], v[14:17], off offset:16
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; GCN-NEXT: global_store_b128 v[8:9], v[10:13], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v8f32.v8i16(<8 x i16> %A, <8 x i16> %B, <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>)
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store <8 x float> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_f32_16x16x16_bf16_imm_non_inlineable(<8 x i16> %A, <8 x i16> %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_f32_16x16x16_bf16_imm_non_inlineable:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_mov_b32_e32 v10, 0x40400000
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
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; GCN-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v12, v10
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; GCN-NEXT: v_dual_mov_b32 v13, v10 :: v_dual_mov_b32 v14, v10
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; GCN-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v16, v10
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; GCN-NEXT: v_mov_b32_e32 v17, v10
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; GCN-NEXT: v_wmma_f32_16x16x16_bf16 v[10:17], v[0:3], v[4:7], v[10:17]
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; GCN-NEXT: s_clause 0x1
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; GCN-NEXT: global_store_b128 v[8:9], v[14:17], off offset:16
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; GCN-NEXT: global_store_b128 v[8:9], v[10:13], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v8f32.v8i16(<8 x i16> %A, <8 x i16> %B, <8 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>)
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store <8 x float> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_f16_16x16x16_f16_imm(<8 x half> %A, <8 x half> %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_f16_16x16x16_f16_imm:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_wmma_f16_16x16x16_f16 v[10:13], v[0:3], v[4:7], 1.0
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; GCN-NEXT: global_store_b128 v[8:9], v[10:13], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v8f16(<8 x half> %A, <8 x half> %B, <8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>, i1 0)
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store <8 x half> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_f16_16x16x16_f16_imm_non_inlineable(<8 x half> %A, <8 x half> %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_f16_16x16x16_f16_imm_non_inlineable:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_mov_b32_e32 v10, 0x42004200
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
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; GCN-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v12, v10
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; GCN-NEXT: v_mov_b32_e32 v13, v10
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; GCN-NEXT: v_wmma_f16_16x16x16_f16 v[10:13], v[0:3], v[4:7], v[10:13]
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; GCN-NEXT: global_store_b128 v[8:9], v[10:13], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v8f16(<8 x half> %A, <8 x half> %B, <8 x half> <half 3.0, half 3.0, half 3.0, half 3.0, half 3.0, half 3.0, half 3.0, half 3.0>, i1 0)
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store <8 x half> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_imm(<8 x i16> %A, <8 x i16> %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_bf16_16x16x16_bf16_imm:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_mov_b32_e32 v10, 0x3f803f80
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
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; GCN-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v12, v10
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; GCN-NEXT: v_mov_b32_e32 v13, v10
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; GCN-NEXT: v_wmma_bf16_16x16x16_bf16 v[10:13], v[0:3], v[4:7], v[10:13]
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; GCN-NEXT: global_store_b128 v[8:9], v[10:13], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v8i16.v8i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> <i16 16256, i16 16256, i16 16256, i16 16256, i16 16256, i16 16256, i16 16256, i16 16256>, i1 0)
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store <8 x i16> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_imm_non_inlineable(<8 x i16> %A, <8 x i16> %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_bf16_16x16x16_bf16_imm_non_inlineable:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_mov_b32_e32 v10, 0x3fc03fc0
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
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; GCN-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v12, v10
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; GCN-NEXT: v_mov_b32_e32 v13, v10
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; GCN-NEXT: v_wmma_bf16_16x16x16_bf16 v[10:13], v[0:3], v[4:7], v[10:13]
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; GCN-NEXT: global_store_b128 v[8:9], v[10:13], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v8i16.v8i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> <i16 16320, i16 16320, i16 16320, i16 16320, i16 16320, i16 16320, i16 16320, i16 16320>, i1 0)
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store <8 x i16> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_imm(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_i32_16x16x16_iu8_imm:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_wmma_i32_16x16x16_iu8 v[6:13], v[0:1], v[2:3], 1
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; GCN-NEXT: s_clause 0x1
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; GCN-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
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; GCN-NEXT: global_store_b128 v[4:5], v[6:9], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v8i32.v2i32(i1 0, <2 x i32> %A, i1 0, <2 x i32> %B, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, i1 0)
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store <8 x i32> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_imm_non_inlineable(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_i32_16x16x16_iu8_imm_non_inlineable:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_mov_b32_e32 v6, 0x80
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
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; GCN-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
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; GCN-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6
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; GCN-NEXT: v_dual_mov_b32 v11, v6 :: v_dual_mov_b32 v12, v6
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; GCN-NEXT: v_mov_b32_e32 v13, v6
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; GCN-NEXT: v_wmma_i32_16x16x16_iu8 v[6:13], v[0:1], v[2:3], v[6:13]
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; GCN-NEXT: s_clause 0x1
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; GCN-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
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; GCN-NEXT: global_store_b128 v[4:5], v[6:9], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v8i32.v2i32(i1 0, <2 x i32> %A, i1 0, <2 x i32> %B, <8 x i32> <i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128>, i1 0)
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store <8 x i32> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_imm(i32 %A, i32 %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_i32_16x16x16_iu4_imm:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_wmma_i32_16x16x16_iu4 v[4:11], v0, v1, 1
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; GCN-NEXT: s_clause 0x1
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; GCN-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16
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; GCN-NEXT: global_store_b128 v[2:3], v[4:7], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v8i32.i32(i1 0, i32 %A, i1 0, i32 %B, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, i1 0)
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store <8 x i32> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_imm_non_inlineable(i32 %A, i32 %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_i32_16x16x16_iu4_imm_non_inlineable:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_mov_b32_e32 v4, 0x80
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
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; GCN-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
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; GCN-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
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; GCN-NEXT: v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v10, v4
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; GCN-NEXT: v_mov_b32_e32 v11, v4
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; GCN-NEXT: v_wmma_i32_16x16x16_iu4 v[4:11], v0, v1, v[4:11]
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; GCN-NEXT: s_clause 0x1
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; GCN-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16
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; GCN-NEXT: global_store_b128 v[2:3], v[4:7], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v8i32.i32(i1 0, i32 %A, i1 0, i32 %B, <8 x i32> <i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128>, i1 0)
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store <8 x i32> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_fp8_imm(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_f32_16x16x16_fp8_fp8_imm:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: v_wmma_f32_16x16x16_fp8_fp8 v[6:13], v[0:1], v[2:3], 1.0
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; GCN-NEXT: s_clause 0x1
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; GCN-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
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; GCN-NEXT: global_store_b128 v[4:5], v[6:9], off
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; GCN-NEXT: s_endpgm
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bb:
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%res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>)
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store <8 x float> %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_fp8_imm_non_inlineable(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {
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; GCN-LABEL: test_wmma_f32_16x16x16_fp8_fp8_imm_non_inlineable:
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; GCN: ; %bb.0: ; %bb
|
|
; GCN-NEXT: v_mov_b32_e32 v6, 0x40400000
|
|
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
|
|
; GCN-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
|
|
; GCN-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6
|
|
; GCN-NEXT: v_dual_mov_b32 v11, v6 :: v_dual_mov_b32 v12, v6
|
|
; GCN-NEXT: v_mov_b32_e32 v13, v6
|
|
; GCN-NEXT: v_wmma_f32_16x16x16_fp8_fp8 v[6:13], v[0:1], v[2:3], v[6:13]
|
|
; GCN-NEXT: s_clause 0x1
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[6:9], off
|
|
; GCN-NEXT: s_endpgm
|
|
bb:
|
|
%res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>)
|
|
store <8 x float> %res, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_fp8_imm(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {
|
|
; GCN-LABEL: test_wmma_f32_16x16x16_bf8_fp8_imm:
|
|
; GCN: ; %bb.0: ; %bb
|
|
; GCN-NEXT: v_wmma_f32_16x16x16_bf8_fp8 v[6:13], v[0:1], v[2:3], 1.0
|
|
; GCN-NEXT: s_clause 0x1
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[6:9], off
|
|
; GCN-NEXT: s_endpgm
|
|
bb:
|
|
%res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>)
|
|
store <8 x float> %res, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_fp8_imm_non_inlineable(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {
|
|
; GCN-LABEL: test_wmma_f32_16x16x16_bf8_fp8_imm_non_inlineable:
|
|
; GCN: ; %bb.0: ; %bb
|
|
; GCN-NEXT: v_mov_b32_e32 v6, 0x40400000
|
|
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
|
|
; GCN-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
|
|
; GCN-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6
|
|
; GCN-NEXT: v_dual_mov_b32 v11, v6 :: v_dual_mov_b32 v12, v6
|
|
; GCN-NEXT: v_mov_b32_e32 v13, v6
|
|
; GCN-NEXT: v_wmma_f32_16x16x16_bf8_fp8 v[6:13], v[0:1], v[2:3], v[6:13]
|
|
; GCN-NEXT: s_clause 0x1
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[6:9], off
|
|
; GCN-NEXT: s_endpgm
|
|
bb:
|
|
%res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>)
|
|
store <8 x float> %res, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_bf8_imm(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {
|
|
; GCN-LABEL: test_wmma_f32_16x16x16_fp8_bf8_imm:
|
|
; GCN: ; %bb.0: ; %bb
|
|
; GCN-NEXT: v_wmma_f32_16x16x16_fp8_bf8 v[6:13], v[0:1], v[2:3], 1.0
|
|
; GCN-NEXT: s_clause 0x1
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[6:9], off
|
|
; GCN-NEXT: s_endpgm
|
|
bb:
|
|
%res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.bf8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>)
|
|
store <8 x float> %res, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_bf8_imm_non_inlineable(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {
|
|
; GCN-LABEL: test_wmma_f32_16x16x16_fp8_bf8_imm_non_inlineable:
|
|
; GCN: ; %bb.0: ; %bb
|
|
; GCN-NEXT: v_mov_b32_e32 v6, 0x40400000
|
|
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
|
|
; GCN-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
|
|
; GCN-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6
|
|
; GCN-NEXT: v_dual_mov_b32 v11, v6 :: v_dual_mov_b32 v12, v6
|
|
; GCN-NEXT: v_mov_b32_e32 v13, v6
|
|
; GCN-NEXT: v_wmma_f32_16x16x16_fp8_bf8 v[6:13], v[0:1], v[2:3], v[6:13]
|
|
; GCN-NEXT: s_clause 0x1
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[6:9], off
|
|
; GCN-NEXT: s_endpgm
|
|
bb:
|
|
%res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.bf8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>)
|
|
store <8 x float> %res, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_bf8_imm(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {
|
|
; GCN-LABEL: test_wmma_f32_16x16x16_bf8_bf8_imm:
|
|
; GCN: ; %bb.0: ; %bb
|
|
; GCN-NEXT: v_wmma_f32_16x16x16_bf8_bf8 v[6:13], v[0:1], v[2:3], 1.0
|
|
; GCN-NEXT: s_clause 0x1
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[6:9], off
|
|
; GCN-NEXT: s_endpgm
|
|
bb:
|
|
%res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>)
|
|
store <8 x float> %res, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_bf8_imm_non_inlineable(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {
|
|
; GCN-LABEL: test_wmma_f32_16x16x16_bf8_bf8_imm_non_inlineable:
|
|
; GCN: ; %bb.0: ; %bb
|
|
; GCN-NEXT: v_mov_b32_e32 v6, 0x40400000
|
|
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
|
|
; GCN-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
|
|
; GCN-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6
|
|
; GCN-NEXT: v_dual_mov_b32 v11, v6 :: v_dual_mov_b32 v12, v6
|
|
; GCN-NEXT: v_mov_b32_e32 v13, v6
|
|
; GCN-NEXT: v_wmma_f32_16x16x16_bf8_bf8 v[6:13], v[0:1], v[2:3], v[6:13]
|
|
; GCN-NEXT: s_clause 0x1
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[6:9], off
|
|
; GCN-NEXT: s_endpgm
|
|
bb:
|
|
%res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>)
|
|
store <8 x float> %res, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_imm(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {
|
|
; GCN-LABEL: test_wmma_i32_16x16x32_iu4_imm:
|
|
; GCN: ; %bb.0: ; %bb
|
|
; GCN-NEXT: v_wmma_i32_16x16x32_iu4 v[6:13], v[0:1], v[2:3], 1
|
|
; GCN-NEXT: s_clause 0x1
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[6:9], off
|
|
; GCN-NEXT: s_endpgm
|
|
bb:
|
|
%res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v8i32.v2i32(i1 0, <2 x i32> %A, i1 0, <2 x i32> %B, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, i1 0)
|
|
store <8 x i32> %res, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_imm_non_inlineable(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {
|
|
; GCN-LABEL: test_wmma_i32_16x16x32_iu4_imm_non_inlineable:
|
|
; GCN: ; %bb.0: ; %bb
|
|
; GCN-NEXT: v_mov_b32_e32 v6, 0x80
|
|
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
|
|
; GCN-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
|
|
; GCN-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6
|
|
; GCN-NEXT: v_dual_mov_b32 v11, v6 :: v_dual_mov_b32 v12, v6
|
|
; GCN-NEXT: v_mov_b32_e32 v13, v6
|
|
; GCN-NEXT: v_wmma_i32_16x16x32_iu4 v[6:13], v[0:1], v[2:3], v[6:13]
|
|
; GCN-NEXT: s_clause 0x1
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
|
|
; GCN-NEXT: global_store_b128 v[4:5], v[6:9], off
|
|
; GCN-NEXT: s_endpgm
|
|
bb:
|
|
%res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v8i32.v2i32(i1 0, <2 x i32> %A, i1 0, <2 x i32> %B, <8 x i32> <i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128>, i1 0)
|
|
store <8 x i32> %res, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16.v8f32.v8f16(<8 x half>, <8 x half>, <8 x float>)
|
|
declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v8f32.v8i16(<8 x i16>, <8 x i16>, <8 x float>)
|
|
declare <8 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v8f16(<8 x half>, <8 x half>, <8 x half>, i1 immarg)
|
|
declare <8 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v8i16.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i1 immarg)
|
|
declare <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v8i32.v2i32(i1 immarg, <2 x i32>, i1 immarg, <2 x i32>, <8 x i32>, i1 immarg)
|
|
declare <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v8i32.i32(i1 immarg, i32, i1 immarg, i32, <8 x i32>, i1 immarg)
|
|
declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8.v8f32.v2i32(<2 x i32>, <2 x i32>, <8 x float>)
|
|
declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.bf8.v8f32.v2i32(<2 x i32>, <2 x i32>, <8 x float>)
|
|
declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v8f32.v2i32(<2 x i32>, <2 x i32>, <8 x float>)
|
|
declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v8f32.v2i32(<2 x i32>, <2 x i32>, <8 x float>)
|
|
declare <8 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v8i32.v2i32(i1 immarg, <2 x i32>, i1 immarg, <2 x i32>, <8 x i32>, i1 immarg)
|
|
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
|
; GFX1170: {{.*}}
|
|
; GFX12: {{.*}}
|