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TheRock/compiler/amd-llvm/llvm/test/CodeGen/ARM/GlobalISel/select-pkhbt.mir
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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# RUN: llc -O0 -mtriple arm-- -mattr=+v6 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,ARM
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+dsp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,THUMB
--- |
define void @test_pkhbt() { ret void }
define void @test_pkhbt_commutative() { ret void }
define void @test_pkhbt_imm16_31() { ret void }
define void @test_pkhbt_unshifted() { ret void }
define void @test_pkhtb_imm16() { ret void }
define void @test_pkhtb_imm1_15() { ret void }
...
---
name: test_pkhbt
# CHECK-LABEL: name: test_pkhbt
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
- { id: 5, class: gprb }
- { id: 6, class: gprb }
- { id: 7, class: gprb }
- { id: 8, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
; ARM-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; ARM-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; THUMB-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; THUMB-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2
%4(s32) = G_CONSTANT i32 7
%5(s32) = G_SHL %1, %4
%6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%7(s32) = G_AND %5, %6
%8(s32) = G_OR %3, %7
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
$r0 = COPY %8(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
...
---
name: test_pkhbt_commutative
# CHECK-LABEL: name: test_pkhbt_commutative
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
- { id: 5, class: gprb }
- { id: 6, class: gprb }
- { id: 7, class: gprb }
- { id: 8, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
; ARM-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; ARM-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; THUMB-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; THUMB-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2
%4(s32) = G_CONSTANT i32 7
%5(s32) = G_SHL %1, %4
%6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%7(s32) = G_AND %5, %6
%8(s32) = G_OR %7, %3
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
$r0 = COPY %8(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
...
---
name: test_pkhbt_imm16_31
# CHECK-LABEL: name: test_pkhbt_imm16_31
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
- { id: 5, class: gprb }
- { id: 6, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
; ARM-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; ARM-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; THUMB-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; THUMB-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2
%4(s32) = G_CONSTANT i32 17
%5(s32) = G_SHL %1, %4
%6(s32) = G_OR %3, %5
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 17, 14 /* CC::al */, $noreg
$r0 = COPY %6(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
...
---
name: test_pkhbt_unshifted
# CHECK-LABEL: name: test_pkhbt_unshifted
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
- { id: 5, class: gprb }
- { id: 6, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
; ARM-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; ARM-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; THUMB-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; THUMB-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2
%4(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%5(s32) = G_AND %1, %4
%6(s32) = G_OR %3, %5
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 0, 14 /* CC::al */, $noreg
$r0 = COPY %6(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
...
---
name: test_pkhtb_imm16
# CHECK-LABEL: name: test_pkhtb_imm16
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
- { id: 5, class: gprb }
- { id: 6, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
; ARM-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; ARM-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; THUMB-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; THUMB-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%3(s32) = G_AND %0, %2
%4(s32) = G_CONSTANT i32 16
%5(s32) = G_LSHR %1, %4
%6(s32) = G_OR %3, %5
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHTB [[VREGX]], [[VREGY]], 16, 14 /* CC::al */, $noreg
$r0 = COPY %6(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
...
---
name: test_pkhtb_imm1_15
# CHECK-LABEL: name: test_pkhtb_imm1_15
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
- { id: 5, class: gprb }
- { id: 6, class: gprb }
- { id: 7, class: gprb }
- { id: 8, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
; ARM-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; ARM-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; THUMB-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; THUMB-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%3(s32) = G_AND %0, %2
%4(s32) = G_CONSTANT i32 7
%5(s32) = G_LSHR %1, %4
%6(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%7(s32) = G_AND %5, %6
%8(s32) = G_OR %3, %7
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHTB [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
$r0 = COPY %8(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
...
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