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TheRock/compiler/amd-llvm/llvm/test/CodeGen/ARM/GlobalISel/thumb-instruction-select-cmp.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
define void @test_icmp_eq_s32() { ret void }
define void @test_icmp_ne_s32() { ret void }
define void @test_icmp_ugt_s32() { ret void }
define void @test_icmp_uge_s32() { ret void }
define void @test_icmp_ult_s32() { ret void }
define void @test_icmp_ule_s32() { ret void }
define void @test_icmp_sgt_s32() { ret void }
define void @test_icmp_sge_s32() { ret void }
define void @test_icmp_slt_s32() { ret void }
define void @test_icmp_sle_s32() { ret void }
...
---
name: test_icmp_eq_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_eq_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 0 /* CC::eq */, $cpsr
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_ne_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ne_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 1 /* CC::ne */, $cpsr
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ne), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_ugt_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ugt_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 8 /* CC::hi */, $cpsr
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ugt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_uge_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_uge_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 2 /* CC::hs */, $cpsr
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(uge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_ult_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ult_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 3 /* CC::lo */, $cpsr
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ult), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_ule_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ule_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 9 /* CC::ls */, $cpsr
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ule), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_sgt_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sgt_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 12 /* CC::gt */, $cpsr
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sgt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_sge_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sge_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 10 /* CC::ge */, $cpsr
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_slt_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_slt_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 11 /* CC::lt */, $cpsr
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(slt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_sle_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sle_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 13 /* CC::le */, $cpsr
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sle), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0
...
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